Samsung Electronics Co., Ltd.

Kwansik Cho

Jinyoung Kim

Beomsuk Lee

Jameyung Kim

Doowon Kwon

Minho Jang

Ho-chul Ji

Dongmo Im

Tae-hun Lee

Dong-Chul Lee

Seokjin Kwon

Sung In Kim

Taeyoung Song

Mangeun Cho

Dongchul Lee

In Ho Ro

Hochul Ji

Sungki Min

An image sensor includes a semiconductor substrate having a first surface and a second surface. The first surface includes an element isolation trench. An element isolation layer is arranged inside the element isolation trench. The element isolation layer defines an active region. A gate electrode is arranged on the first surface of the semiconductor substrate. An interlayer insulating layer is arranged on the first surface of the semiconductor substrate and covers the gate electrode. A ground contact is configured to penetrate the element isolation layer and the interlayer insulating layer and contacts the semiconductor substrate. A color filter is arranged on the second surface of the semiconductor substrate.

Image sensor

An image sensor includes a first chip including a pixel region, a pad region, and an optical black region interposed between the pixel region and the pad region, and a second chip being in contact with a first surface of the first chip and including circuits for driving the first chip. The first chip includes a first substrate, a device isolation portion disposed in the first substrate and defining unit pixels, an interlayer insulating layer interposed between the first substrate and the second chip, a connection wiring structure disposed in the interlayer insulating layer, and a connection contact plug disposed in the interlayer insulating layer and connecting the connection wiring structure to the device isolation portion in the optical black region. The image sensor further includes a conductive pad disposed in the first chip or the second chip.

An image sensor includes a substrate, and a pixel separation pattern disposed in the substrate and interposed between a plurality of unit pixels. The plurality of unit pixels include a first unit pixel region and a second unit pixel region adjacent to the first unit pixel region in a first direction. The first unit pixel region and the second unit pixel region respectively include a first transfer gate and a second transfer gate. The pixel separation pattern includes a first pixel separation part interposed between the first unit pixel region and the second unit pixel region, and a second pixel separation part spaced apart from the first pixel separation part in the first direction. A top surface of the first pixel separation part is lower than a top surface of the second pixel separation part.

An image sensor may include a substrate having first and second surfaces opposite to each other and including unit pixel regions and impurity regions near the first surface, a device isolation pattern provided on the first surface to define the impurity regions, and an interconnection layer including an insulating layer covering the first surface of the substrate, interconnection lines on the insulating layer, and a penetration structure penetrating the insulating layer. The penetration structure may include a first pattern connected to one of the impurity regions and in contact with at least a portion of the device isolation pattern, a second pattern provided on the first pattern and in contact with the interconnection lines, and a third pattern provided between the first and second patterns. A top surface of the first pattern may be higher than that of the device isolation pattern.

Image sensor with increased gate pattern width

An image sensor including a semiconductor substrate having a first surface and a second surface, and a pixel region having a photoelectric conversion region; a first conductive pattern in a first trench defining the pixel region and extending from the first surface toward the second surface; a second conductive pattern in a second trench shallower than the first trench and defined between a plurality of active patterns on the first surface of the pixel region; a transfer transistor and a plurality of logic transistors on the active patterns; and a conductive line on the second surface and electrically connected to the first conductive pattern.

Growing community of inventors

Hwaseong-si, South Korea

Kwansik Cho