Nvidia Corporation

Kwanjee Ng

Padam Patt Krishnani

Dong-Myung Choi

Anu Subbaraman

Supreet Agrawal

Madhusudhan Sarda

Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source. The method includes masking the output signals to generate respective masked output signals, and applying the masked output signals to SoC circuit elements to prevent from transitioning into low power states and hence keeping the debug logic circuitry alive. The method includes debugging the finite state machine in the lowest power state by the debug logic circuit.

Methods and apparatus for debugging lowest power states in System-On-Chips

A window-enabled TDC and method of detecting phase of a reference signal. One embodiment of the window-enabled TDC includes: (1) a window generator configured to receive a reference signal and a clock signal, and (2) a TDC circuit coupled to the window generator and configured to be enabled based on the reference signal and disabled based on the clock signal.

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Cupertino, CA, United States of America

Kwanjee Ng