Samsung Electronics Co., Ltd.

Kwangyoung Jung

Jeehoon Han

Kohji Kanamori

Sangyoun Jo

Joonhee Lee

Jongwon Kim

Dongseog Eun

Giyong Chung

Junghwan Park

Jaeryong Sim

Sanghun Chun

Seunghun Kim

Jiho Uh

Youngji Noh

Donghoon Park

Jung-Soon Bok

WonHee Yoon

Jaebok Baek

Hyunjoon Ohn

Provided is a plasma generating system including: a resonant inverter including a switching circuit and configured to generate a device output current and a device output voltage, and to have a switching frequency based on an input DC current and an input DC voltage; a plasma source configured to generate a plasma based on the device output current and the device output voltage; a controller configured to control the switching frequency of the resonant inverter based on a value of the input DC current, a value of the input DC voltage, a value of the device output current, and a value of the device output voltage; and a junction temperature estimator configured to: estimate a current output from the switching circuit based on the value of the input DC voltage, the value of the device output current, and the value of the device output voltage, generate an inverted current estimate value, and estimate a junction temperature of the switching circuit based on the inverted current estimate value.

Junction temperature estimation device and plasma generating system including the same

A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

Semiconductor device

A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

Semiconductor device having dummy structures in a peripheral region and data storage system including the same

A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

Semiconductor devices comprising crack preventing layers and data storage systems including the same

A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

Three-dimensional (3D) semiconductor memory device

A semiconductor device includes a gate electrode structure, a channel, first division patterns, and a second division pattern. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each gate electrode extends in a second direction parallel to the substrate. The channel extends in the first direction through the gate electrode structure. The first division patterns are spaced apart from each other in the second direction, and each first division pattern extends in the second direction through the gate electrode structure. The second division pattern is between the first division patterns, and the second division pattern and the first division patterns together divide a first gate electrode in a third direction parallel to the substrate and crossing the second direction. The second division pattern has an outer contour that is a curve in a plan view.

Semiconductor device, method of manufacturing the same, and massive data storage system including the same

Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

Growing community of inventors

Hwaseong-si, South Korea

Kwangyoung Jung