Samsung Electronics Co., Ltd.

Kwangsook Noh

Hijung Kim

Jaepil Lee

Kwangchol Choe

A semiconductor device includes an element region including a semiconductor substrate and a plurality of elements formed on the semiconductor substrate and a wiring region disposed on the element region and including an interlayer insulating layer, a plurality of wiring patterns in the interlayer insulating layer, and a via structure extending in a first direction, perpendicular to an upper surface of the semiconductor substrate in the interlayer insulating layer, wherein the plurality of elements include a first input/output circuit transmitting and receiving a first signal and a second I/O circuit transmitting and receiving a second signal, different from the first signal, the plurality of wiring patterns is a coil pattern includes an inductor circuit, the coil pattern is connected to the first I/O circuit, and the via structure passes through a center of the coil pattern and is connected to the second I/O circuit.

Semiconductor device, semiconductor package, and memory system

A memory chip includes a plurality of storage blocks respectively including a plurality of memory cells; and a logic circuit configured to control the plurality of storage blocks, wherein the logic circuit includes an input/output pad configured to input data to the plurality of storage blocks and output data to the plurality of storage blocks; wherein the logic circuit is further configured to allocate block address codes having a bit inversion relationship with each other, output a mode selection signal in response to external control, output an external address code in response to the mode selection signal indicating a first addressing mode, and output an address code having a bit inversion relationship with regard to the external address code in response to the mode selection signal indicating a second addressing mode, and select a storage block to be controlled by the access command from among the plurality of storage blocks.

Memory chip and memory system including the same

A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

Growing community of inventors

Suwon-si, South Korea

Kwangsook Noh