Cadence Design Systems, Inc.

Kwangsoo Han

Zhuo Li

Charles Jay Alpert

Thomas Andrew Newton

William Robert Reece

Amin Farshidi

Michael Alexander

Jordan Moxon

Zi Wang

Various embodiments provide for modifying a circuit design based on timing tradeoff, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a return on investment (ROI) concept to determine one or more thresholds for how much area or power of a circuit design should be available for use (e.g., sacrificed) in order to obtain an improvement in slack by a given transformation.

Circuit design modification based on timing tradeoff

Aspects of the present disclosure address systems and methods for applying logic sharing transformations to integrated circuit designs. Consistent with some embodiments, a cube-literal matrix is generated for an integrated circuit design. The cube-literal matrix comprises a non-unique matrix representation of functional logic in the integrated circuit design. A candidate cube is extracted from the cube-literal matrix to evaluate for application of a logic sharing transformation. The candidate cube comprises a sub-matrix of the cube-literal matrix corresponding to two or more common inputs of two or more logical operators. Based on determining that application of the logic sharing transformation to the candidate cube results in a reduction to a literal count in the integrated circuit design, the cube-literal matrix is updated to reflect the application of the logic sharing transformation to the candidate cube and the integrated circuit design is updated based on the updated cube-literal matrix.

Logic sharing maximization using non-unique matrix representation

Electronic design automation systems, methods, and media are presented for multi-dimension clock gate design in clock tree synthesis. In one embodiment, an input list of clock gate types is accessed, and the list is then used in generating a clock gate matrix. A circuit design with a clock tree is then accessed. The multi-dimensional design involves automatically selecting, for a first clock gate of the routing tree, a first clock gate type from the clock gate matrix based on a size and associated area for the first clock gate type to select a drive strength value for the first clock gate in the routing tree. The first clock gate is then resized to generate a resized first clock gate using the clock gate matrix to adjust a first delay value associated with the first clock gate while maintaining the drive strength value.

Multi-dimension clock gate design in clock tree synthesis

Electronic design automation systems, methods, and media are presented for a waveform propagation timing model for use with circuit designs and electronic design automation (EDA). One embodiment involves generating a gate output waveform for a circuit element using a driver input signal waveform and then generating a circuit element output waveform using the gate output waveform and an N-pole model of an interconnect with the first circuit element using moment matching. Timing values are then determined from the circuit element output waveform, such as delay and slew values. This waveform may then be propagated through the circuit, and an updated design generated using the timing values estimated from the modeled waveforms.

Waveform propagation timing modeling for circuit design

Electronic design automation systems, methods, and media are presented for view pruning to increase the efficiency of computing operations for analyzing and updating a circuit design for an integrated circuit. One embodiment involves accessing a circuit design stored in memory that is associated with a plurality of views, selecting a first view of the plurality of view for view pruning analysis, and identifying a plurality of input values for the first view of the plurality of views. Random nets are generated based on the views, view inputs, and pruning thresholds. Certain views are then selected as dominant based on a comparison of the output slews different nets and views. Subsequent analysis is then performed and used to update the design without using the pruned views (e.g., using the selected dominant views).

View pruning for routing tree optimization

Aspects of the present disclosure address systems and methods for dynamically adjusting skew windows during clock tree synthesis (CTS). A method may include identifying a pin insertion delay (PID) assigned to a clock sink in a set of clock sinks of a buffer tree in an integrated circuit design. The method further includes determining a skew window for the clock sink based on a skew target and adjusting the skew window based on identifying the PID assigned to the clock sink. The skew window is adjusted based on a skew adjustment parameter. The method further includes building a clock tree based on the buffer tree and the adjusted skew window. The building of the clock tree comprises tuning a clock path delay of the clock sink according to the adjusted skew window. A layout instance may be generated for the IC design based in part on the clock tree.

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Austin, TX, United States of America

Kwangsoo Han