Cambridge Silicon Radio Limited

Kwangseok Han

Rainer Herberholz

James Digby Yarlet Collier

Simon Chang

Luca Milani

Steve Jones

Justin Penfold

Stuart Aitken

Marco Bruno

Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.

Control circuitry for memory cells

Apparatus for controlling the generation of a DC signal at the output of a mixer, so that the DC signal is predictable, enabling a static offset compensation voltage to offset the DC signal. The apparatus comprises a mixer configured to receive a first and a second input signal, the mixer being such as to generate a first DC signal at the output of the mixer when the first and second input signals have the same frequency and a first relative phase, a phase detector for determining the relative phase of the first and second signals, and a phase modifier configured to modify the phase of the second signal relative to the first signal in dependence on the determination of the relative phase between the first and second signals such that the resulting DC signal at the output of the mixer is the first DC signal.

Architecture to remove a bimodal dynamic DC offset in direct conversion receiver

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Cambridge, United Kingdom

Kwangseok Han