Himax Imaging, Inc.

Kwangoh Kim

Amit Mittra

Youngchul Sohn

Hack Soo Oh

Satya Narayan Mishra

Ping Hung Yin

Kaveh Moazzami

An anti-eclipse circuit for use in an imager includes a differential amplifier and a feedback circuit. The differential amplifier is coupled to an output line for receiving an output signal associated with the voltage level of a floating diffusion region in a pixel of the imager and configured to detect when a reset signal received from the pixel drops below a predetermined level. The feedback circuit is configured to increase the reset signal when the output signal is lower than the clamp voltage, thereby keeping the reset signal at the constant level.

Anti-eclipse circuit and related imager

A digital double-sampling (DDS) circuit includes a comparator with input nodes respectively connected to a ramp voltage and an image output node of a pixel circuit via a capacitor; a reset switch connected between the input nodes for resetting the capacitor; an analog-to-digital converter (ADC) coupled to receive a comparison output of the comparator, the ADC including a counter that counts while the ramp voltage is ramping, thereby generating a reset-ADC value in a reset phase and generating a signal-ADC value in a signal phase; a subtractor that subtracts the reset-ADC value from the signal-ADC value, thereby resulting in a difference value representing a sampled output; and a clamp circuit that generates a clamp voltage at the image output node. In the reset phase, the clamp circuit is disabled after the capacitor finishes resetting but before the ramp voltage begins ramping.

Digital double sampling circuit

An analog block implemented with a band-gap reference scheme for use in a device includes a mode control unit and a band-gap reference circuit. The mode control unit is configured to generate a mode selection signal associated with the operational mode of the device. The band-gap reference circuit includes a bias generator, an error amplifier, and a band-gap loop circuit. The bias generator is configured to provide a band-gap reference voltage in a first bias state when the device operates in a normal mode or in a second bias state when the device operates in a standby mode. The error amplifier is configured to generate an error voltage according to the bias voltage. The band-gap loop circuit is configured to provide a band-gap reference voltage according to the error voltage. First current flowing through the bias generator in the first bias state is larger than second current flowing through the bias generator in the second bias state.

Analog block implemented with band-gap reference scheme and related driving method

An image processing system for an image sensor includes an analog-to-digital conversion (ADC) unit that performs ADC on pixel signals, thereby generating digital pixel signals; a correlated double sampling (CDS) unit that performs CDS on the digital pixel signals; a black level estimation (BLE) unit that generates a negative offset voltage according to dark voltage obtained from CDS performed on estimating optical black pixels (OBPs) of a pixel array, the negative offset voltage being subtracted from the pixel signals before feeding the pixel signals to the ADC unit; and a black level compensation (BLC) unit that performs BLC on active pixels sensors (APSs) and the compensating OBPs of the pixel array.

Image processing system and method for an image sensor

A method to read out pixels includes reading a first pixel by resetting a first photodetector, integrating the first photodetector after resetting the first photodetector, resetting a first floating diffusion node coupled to the first photodetector and a second floating diffusion node coupled to a second photodetector, transferring charge from the first photodetector to the first floating diffusion node, comparing a first signal at the first floating diffusion node and a second signal at the second floating diffusion node and generating a first signal to latch a first counter value when the first signal is less than the second signal, incrementing the first signal and decrementing the second signal, and comparing the first signal and the second signal and generating a second signal to latch a second counter value when the first signal is greater than the second signal, wherein the difference between the second counter value and the first counter value indicates a first pixel level.

Growing community of inventors

Tainan, Taiwan

Kwangoh Kim