Samsung Electronics Co., Ltd.

Kwangmin Park

Kihyun Hwang

Juyul Lee

Sunghoi Hur

Hanmei Choi

Chanjin Park

Toshiro Nakanishi

Wansik Hwang

Kwang Soo Seol

Dongchul Yoo

Jonguk Kim

Dongsung Choi

Dongho Ahn

Jeonghee Park

Jaeho Jung

Seungjae Baik

Juwan Lim

Jinwoo Lee

Jaeyoung Ahn

Zhe Wu

Chungman Kim

Jiho Park

Byongju Kim

Jumi Yun

Jae-young Ahn

Changseung Lee

Wooyoung Yang

Siyoung Choi

Bio Kim

Young-Min Ko

Changyup Park

Young-jin Noh

Bonwon Koo

Sungkweon Baek

Minwoo Choi

Hajun Sung

Jongsik Chun

Bumsu Kim

Wonjun Lee

Ki-Hyun Hwang

Hideki Horii

Ji-Hoon Choi

Jeong-Hee Park

Kwang-Soo Seol

Jeongho Park

Jong-Uk Kim

SeungHyun Lim

Gyuhwan Oh

Hyun Kyu Park

Gukhyon Yon

Byong-Hyun Jang

Ja Bin Lee

Hyun Ku Park

Wonjun Park

Seung-Geun Yu

Seunggeun Yu

Gwangguk An

Ju-Yul Lee

Youngmin Ko

Segab Kwon

Jabin Lee

Jungmoo Lee

Jaeheung Lim

Sihoon Lee

JaeHo Choi

Sukhwan Chung

Hwasung Chae

A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

Semiconductor device including chalcogen compound and semiconductor apparatus including the same

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Three-dimensional semiconductor memory devices and methods of fabricating the same

A variable resistance memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction and crossing the first conductive lines in a plan view, and cell structures respectively provided at crossing points of the first conductive lines and the second conductive lines in the plan view. Each of the cell structures includes a switching pattern, a variable resistance pattern, and a first electrode provided between the switching pattern and the first conductive line, the first electrode including carbon. Each of the first conductive lines includes an upper pattern including a metal nitride in an upper portion thereof. The upper pattern is in contact with a bottom surface of the first electrode.

Variable resistance memory device and method of manufacturing the same

A gas sensor includes a piezoelectric substrate; a resonator in an electrode region on an upper surface of the piezoelectric substrate, the resonator including interdigital transducer (IDT) electrodes and IDT pads connected to the IDT electrodes, the IDT electrodes configured to generate a surface acoustic wave in a center region of the electrode region, the surface acoustic wave propagating in a first horizontal direction; a sensing film in the center region of the electrode region on the upper surface of the piezoelectric substrate, the sensing film including a sensing material that interacts with a target gas; and a heater in an edge region surrounding the electrode region on the upper surface of the piezoelectric substrate, the heater including heater electrodes configured to heat the sensing film and heater pads connected to the heater electrodes, the heater electrodes and the heater pads forming a closed conduction loop.

Gas sensor, sensor array module and mobile device including the same

Semiconductor device including layers with different chalcogen compounds and semiconductor apparatus including the same

A semiconductor device and a method of forming the same are provided. The semiconductor device including a first conductive line on a substrate, memory cell structures stacked on the first conductive line, a second conductive line between the memory cell structures; and a third conductive line on the memory cell structures may be provided. Each of the plurality of memory cell structures includes a data storage material pattern, a switching material pattern, and a plurality of electrode patterns, at least one of the electrode patterns includes at least one of carbon material layer or a carbon-containing material layer, and the at least one of the electrode patterns includes a first region doped with a nitrogen and a second region that is not doped with the nitrogen, or is doped with the nitrogen at a first concentration lower than a second concentration of the nitrogen in the first region.

Semiconductor device and method of forming the same

A variable resistance memory device includes a plurality of memory cells arranged on a substrate. Each of the memory cells includes a selection element pattern and a variable resistance pattern stacked on the substrate. The selection element pattern includes a first selection element pattern having a chalcogenide material and a second selection element pattern having a metal oxide and coupled to the first selection element pattern.

Variable resistance memory device

A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

Semiconductor device

A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.

Semiconductor device including data storage material pattern

A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 &#x3bc;s to about 54 &#x3bc;s.

Method of fabricating a variable resistance memory device

A memory device including a first conductive line on a substrate and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and a memory cell between the first conductive line and the second conductive line, the memory cell including a variable resistance memory layer, a buffer resistance layer, and a switch material pattern, extending in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, and having a tapered shape with a decreasing horizontal width along the vertical direction, wherein at least a part of the variable resistance memory layer and at least a part of the buffer resistance layer of the memory cell are at a same vertical level.

Memory devices

A method of fabricating a variable resistance memory device that includes forming a plurality of memory cells on a substrate. Each of the plurality of memory cells in a switching device and a variable resistance pattern. A capping structure is formed that commonly covers lateral side surfaces of the plurality of memory cells. An insulating gapfill layer is formed that covers the capping structure and fills a region between adjacent memory cells of the plurality of memory cells. The forming of the capping structure includes forming a second capping layer including silicon oxide that covers the lateral side surfaces of the plurality of memory cells. At least a partial portion of the second capping layer is nitrided by performing a first decoupled plasma process to form a third capping layer that includes silicon oxynitride.

Variable resistance memory device and method of fabricating the same

A semiconductor device includes a base structure comprising a semiconductor substrate, a first conductive structure disposed on the base structure, and extending in a first direction, the first conductive structure including lower layers, and at least one among the lower layers including carbon, and a data storage pattern disposed on the first conductive structure. The semiconductor device further includes an intermediate conductive pattern disposed on the data storage pattern, and including intermediate layers, at least one among the intermediate layers including carbon, a switching pattern disposed on the intermediate conductive pattern, and a switching upper electrode pattern disposed on the switching pattern, and including carbon. The semiconductor device further includes a second conductive structure disposed on the switching upper electrode pattern, and extending in a second direction intersecting the first direction, and a hole spacer disposed on a side surface of the data storage pattern.

A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.

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Seoul, South Korea

Kwangmin Park