Samsung Electronics Co., Ltd.

Kwangjin Moon

Jinnam Kim

Hoonjoo Na

Taeseong Kim

Byung Lyul Park

Hakseung Lee

Sukchul Bang

Hyungjun Jeon

Hyoukyung Cho

Jin Ho An

Seokho Kim

JuBin Seo

Sujeong Park

Kunsang Park

Myungjoo Park

Gilheyun Choi

Dosun Lee

Jaewon Hwang

Ho-jin Lee

Ju-Il Choi

Hojin Lee

Dong-Chan Lim

SungHee Kang

Atsushi Fujisaki

Deok-Young Jung

Jaehyung Park

Kyuha Lee

Yeun-Sang Park

Joohee Jang

Pilkyu Kang

Byung-Lyul Park

Jae-Hwa Park

Naein Lee

Taeyeong Kim

Yi Koan Hong

Seongmin Son

Eunsuk Jung

Sonkwan Hwang

Pil-Kyu Kang

Sangjun Park

Jeonggi Jin

Kyu-ha Lee

Dong-chan Lim

Eunji Kim

Jun Hyung Kim

Ho-Jin Lee

Seungha Oh

Deokyoung Jung

Jisoon Park

Minsoo Han

Hyoju Kim

Yikoan Hong

Daesuk Lee

Sukyoung Kim

Sohye Cho

Kiyoung Yun

Yeonglyeol Park

Kisoon Bae

A semiconductor package includes a first semiconductor chip including first pads and a first insulating layer, and a second semiconductor chip including second upper pads, a second insulating layer, second lower pads, and through electrodes connecting the second upper pads and the second lower pads to each other. The package includes a third semiconductor chip including third upper pads, an upper barrier layer, a third insulating layer, third lower pads, a lower barrier layer, and dummy electrode structures connecting the third upper pads and the third lower pads to each other. The package includes an encapsulant below the first semiconductor chip to seal at least a portion of each of the second and third semiconductor chips and cover side surfaces of the third lower pads. The package includes bump structures below the encapsulant and the second and third semiconductor chips.

Semiconductor device including through electrodes

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

Semiconductor device

A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite from each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via extending from the second surface of the first semiconductor substrate and into at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.

Semiconductor devices having penetration vias

An integrated circuit device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first insulating layer on the first surface of the semiconductor substrate, an electrode landing pad positioned on the first surface of the semiconductor substrate and having a sidewall surrounded by the first insulating layer, a top surface apart from the first surface of the semiconductor substrate, and a bottom surface opposite to the top surface, and a through-electrode configured to penetrate through the semiconductor substrate and contact the top surface of the electrode landing pad, wherein a horizontal width of the top surface of the electrode landing pad is less than a horizontal width of the bottom surface of the electrode landing pad and greater than a horizontal width of a bottom surface of the through-electrode in contact with the top surface of the electrode landing pad.

Integrated circuit device with through-electrode and electrode landing pad, and semiconductor package including the same

A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.

Semiconductor packages

A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

Semiconductor packages and methods of manufacturing the semiconductor packages

A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

Semiconductor device including penetration via structure

A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nmetal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nmetal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nmetal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

Semiconductor device including through via structure

A semiconductor device includes: a semiconductor substrate having opposing first side and second sides; an active region and an isolation region on the first side; a circuit device on the active region; a front side interconnection structure on the first side and including front side interconnection layers disposed on different levels; first and second back side interconnection structures below the second side; a buried structure having a portion disposed in the isolation region and including a conductive line; a first through-electrode structure including a first through-electrode contacting the conductive line and penetrating the semiconductor substrate between the conductive line and the first back side interconnection structure; and a second through-electrode structure including a second through-electrode penetrating the semiconductor substrate between a first front side interconnection layer and the second back side interconnection structure. The first front side interconnection layer is on a level higher than that of the conductive line.

Semiconductor device including through-electrodes

An integrated circuit semiconductor device includes a substrate including a first surface and a second surface opposite the first surface, a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate, a through silicon via (TSV) landing part in the trench, the TSV landing part having a first portion spaced apart from the first surface of the substrate, and a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion, a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part, and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part.

Integrated circuit semiconductor device including through silicon via

A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

Disclosed is a semiconductor device comprising a semiconductor substrate, an under-bump pattern on the semiconductor substrate and including a first metal, a bump pattern on the under-bump pattern, and an organic dielectric layer on the semiconductor substrate and in contact with a sidewall of the bump pattern. The bump pattern includes a support pattern in contact with the under-bump pattern and having a first width, and a solder pillar pattern on the support pattern and having a second width. The first width is greater than the second width. The support pattern includes at least one of a solder material and an intermetallic compound (IMC). The intermetallic compound includes the first metal and the solder material.

A semiconductor package includes a first structure including a first semiconductor chip, and a second structure on the first structure. The second structure includes a second semiconductor chip, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern.

A semiconductor device includes a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate, and a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer. The first and second bonding layers are in contact with each other, and each of the first and second adsorption layers includes a low-&#x3ba; dielectric material.

Method of manufacturing a semiconductor device including bonding layer and adsorption layer

Semiconductor packages stacked by wafer bonding process and methods of manufacturing the semiconductor packages

Growing community of inventors

Hwaseong-si, South Korea

Kwangjin Moon