Samsung Electronics Co., Ltd.

Gwangju Institute of Science and Technology

Lg Electronics Inc.

California Institute of Technology

University of California

Samsung Corning Co., Ltd.

Kwanghee Lee

Sangwook Kim

Jinseong Heo

Seunghoon Han

Changgyun Shin

Seunggeol Nam

Taehwan Moon

Andrei Faraon

Amir Arbabi

Yongsung Kim

Taehan Kim

Bumsuk Kim

Yu Horie

Jeongyub Lee

Sungha Choi

Uihui Kwon

Minsu Kim

Byungjoo Lee

Jaeho Kim

Wook Su Lee

Sang-Yoon Lee

Alan J Heeger

Kyung-Eun Byun

Jae Ho Kim

Yunseong Lee

Keunwook Shin

Kgiwung Ryoo

Hongkyu Kang

Hagyoul Bae

Yunki Lee

Dongmin Keum

Yongwan Jin

Chongook Yoon

Seoung-Ho Lee

Taewan Kim

Lilong Shi

JungChak Ahn

Do-Han Kim

Insu Choi

Dae-Jeong Kim

Changmin Lee

Wonjae Shin

Jae-Suk Lee

Sung-Joon Kim

Tae-Kyeong Ko

Jongbaek Seon

Deokho Seo

Namsu Lee

Sangwoo Han

Do-hwan Kim

Yongwoo Jeon

Jeeeun Yang

Jongmin Park

Moonil Jung

Yuseok Yang

Junsung Park

Cholmin Kim

Shinuk Cho

Chang-Lyoul Lee

Sung-Heum Park

Sung Heum Park

Yoonsuk Kim

Kanghyun Baek

Jiyong Lee

Junghwan Kim

Inwook Hwang

Geunjin Kim

Jihoon Rhee

Daechul Park

Hyundam Jung

Jong-Hoon Lee

Song-Yi Jeong

Euiyoung Song

Yeaju Jang

Kilho Yu

Byoungwook Park

Jae-Kwan Lee

Nara Kim

Seyoung Kee

Beom-Goo Kang

Euntae Kim

An image sensor includes a pixel array in which a plurality of normal pixels and a plurality of autofocus (AF) pixels are disposed, and a logic circuit. The logic circuit provides an autofocus function using a phase difference between pixel signals obtained from each of the plurality of AF pixels. Each of the AF pixels includes a single AF lens disposed on a pair of pixel areas. An AF lens of the AF pixel spaced apart from a center of the pixel array may have an area larger than an area of the AF lens of the AF pixel adjacent to the center.

Image sensor with size-variable autofocus lenses

Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

Complementary metal oxide semiconductor device

The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

Oxide semiconductor transistor, method of manufacturing the same, and memory device including oxide semiconductor transistor

A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

Semiconductor device

An image sensor includes a first light sensor layer including light sensing cells configured to sense first light of an incident light and generate electrical signals based on the sensed first light, and a color filter array layer disposed on the first light sensor layer, and including color filters respectively facing the light sensing cells. The image sensor further includes a second light sensor layer disposed on the color filter array layer, and configured to sense second light of the incident light and generate an electrical signal based on the sensed second light. Each of the color filters includes a nanostructure including a first material having a first refractive index, and a second material having a second refractive index greater than the first refractive index, the first material and the second material being alternately disposed with a period.

Image sensor including nanostructure color filter

A pixel array of an image sensor includes a plurality of pixel groups. Each pixel group includes a plurality of unit pixels adjacent to each other and respectively including photoelectric conversion elements disposed in a semiconductor substrate, a color filter shared by the plurality of unit pixels, and a plurality of microlenses disposed on the color filter and having sizes different from each other such that the plurality of microlenses respectively focus an incident light to the photoelectric conversion elements included in the plurality of unit pixels. Deviations of sensing sensitivity of unit pixels are reduced and quality of images captured by the image sensor is enhanced by adjusting sizes of microlenses.

Pixel array of image sensor and method of manufacturing the same

An oxide semiconductor transistor includes: an insulating substrate including a trench; a gate electrode in the trench; an oxide semiconductor layer on a surface of the insulating substrate, the surface exposed through the trench; and a ferroelectric layer between the gate electrode and the oxide semiconductor layer, wherein the oxide semiconductor layer may include a source region and a drain region which are on the insulating substrate outside the trench and are apart from each other with the gate electrode therebetween.

Oxide semiconductor transistor

A method of guiding a semiconductor manufacturing process includes receiving semiconductor manufacturing process data corresponding to a target semiconductor product, generating first semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a technology computer-aided design (TCAD) model trained through machine learning based on training data including TCAD simulation data, generating second semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a compact model generated based on information of measurement of at least one semiconductor characteristic of a first semiconductor product, generating, based on the first semiconductor characteristic data and the second semiconductor characteristic data, a plurality of process policies respectively corresponding to a plurality of strategic references, by using a plurality of strategy models; and providing a final process policy corresponding to the target semiconductor product based on the plurality of process policies.

Method and electronic device for guiding semiconductor manufacturing process

An image sensor may include a semiconductor substrate having a light receiving surface thereon and a plurality of spaced-apart semiconductor photoelectric conversion regions at adjacent locations therein. A grating structure is provided on the light receiving surface. This grating structure extends opposite each of the plurality of spaced-apart photoelectric conversion regions. An optically-transparent layer is provided on the grating structure. This grating structure includes a plurality of spaced-apart grating patterns, which can have the same height and the same width. In addition, the grating patterns may be spaced apart from each other by a uniform distance. The grating structure is configured to selectively produce &#xb1;1 or higher order diffraction lights to the photoelectric conversion regions, in response to light incident thereon.

Image sensors having grating structures therein that provide enhanced diffraction of incident light

A field-effect transistor includes a gate structure comprising a structure in which a first insulating layer, a first gate electrode, and a second insulating layer are sequentially stacked on a first conductive layer, the gate structure surrounding a first hole through the first insulating layer and exposing a part of the first conductive layer; a second conductive layer on the second insulating layer and surrounding a second hole connected to the first hole and exposing a part of the first conductive layer; a first gate insulating layer covering an inner wall of the gate structure exposed by the first hole; a semiconductor layer covering a part of the first conductive layer exposed through the first hole and the second hole, the first gate insulating layer, and the second conductive layer; a second gate insulating layer covering the semiconductor layer; and a second gate electrode filling the first and second holes.

Field-effect transistor, field-effect transistor array structure and method of manufacturing field-effect transistor

A semiconductor memory device for a hash solution includes a hashing logic block including a plurality of hashing logics configured to perform a hash function, a memory cell block including a plurality of memory cells, and an input/output (I/O) control structure configured to change a data interface between the hashing logic block and the memory cell block based on a characteristic of the hash function to be performed.

Semiconductor memory device for hash solution and method of driving the same

A storage module includes a dynamic random access memory (DRAM) device, a nonvolatile memory device, and a high-speed buffer memory. An method of operating the storage module includes copying target data stored in the nonvolatile memory device to the high-speed buffer memory in response to an external device entering a page fault mode, receiving a first refresh command from the external device, and, in response to the first refresh command, performing a first refresh operation associated with the DRAM device and moving the target data copied to the high-speed buffer memory to the DRAM device during a first refresh reference time.

Storage modules, methods of operating a storage module, and methods of operating a host controlling a storage module

Disclosed are a p-doped conjugated small molecular electrolyte containing a compound represented by Formula 1 and an organic electronic device using the same as a hole transport material.[Ar&#x2014;Ar&#x2014;Ar]&#x2003;&#x2003;&#x3c;Formula 1&#x3e; wherein, in Formula 1, Aris any one selected from the following Compound Group 1, Aris any one selected from the following Compound Group 2a or the following Compound Group 2b, and superscript '+' in the square bracket indicates an oxidized portion of a main chain of the small molecule.

P-doped conjugated small molecular electrolyte and organic electronic devices using the same

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Gwangju, South Korea

Kwanghee Lee