Samsung Electronics Co., Ltd.

Kwang-Wook Koh

Sung-Ho Kim

Nae-in Lee

Jin-Hee Kim

Sung-Chul Park

In-Wook Cho

Ju-Ri Kim

Jae-Hwang Kim

Chang-Hun Lee

Ki-chul Kim

Sang-Su Kim

Hee-Seog Jeon

Seung-Beom Yoon

Geum-jong Bae

Geum-Jong Bae

Sang Su Kim

Ki Chul Kim

Jeong-Uk Han

Seung-Jin Yang

Byou-Ree Lim

In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Methods of forming nonvolatile memory devices

An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Electrically erasable programmable read-only memory (EEPROM) device and methods of fabricating the same

In a nonvolatile memory device and a method of fabricating the same, the nonvolatile memory device may include a semiconductor substrate having a device isolation layer defining an active region, a pair of nonvolatile memory transistors on the active region, a select transistor disposed between the pair of nonvolatile memory transistors, and floating diffusion regions on the active region between each of the nonvolatile memory transistors and the select transistor. The select transistor may include a gate insulation layer having a thickness and a material that are the same as those of gate insulation layers of the nonvolatile memory transistors. The resulting nonvolatile memory device may include a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Nonvolatile memory devices and methods of forming the same

In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

Non-volatile memory device and methods of forming and operating the same

A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

Programming method of a non-volatile memory device having a charge storage layer between a gate electrode and a semiconductor substrate

A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same

A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

Method of manufacturing a non-volatile semiconductor memory device

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Seoul, South Korea

Kwang-Wook Koh