Samsung Electronics Co., Ltd.

S-printing Solution Co., Ltd.

Kwang-woo Lee

Daewon Ha

Gwan-Hyeob Koh

Dae-Hwan Kang

Dae-Jeong Kim

Kyu-Rie Sim

Heon Gwon Lee

Han-bin Noh

Jae-Hee Oh

Jae-Hyun Yeo

Chang-Wook Jeong

Jung Hyuk Lee

Ilmok Park

Seulji Song

Kyusul Park

Young-Joo Jeon

Inho Cho

Jae-Suk Kwon

Eun-Seong Lee

Hoon-Chang Yang

Kabyong Kim

A method of operating a resistive memory device to increase a read margin includes applying a write pulse to a memory cell such that the memory cell is programmed to a target resistance state, and applying a post-write pulse to the memory cell to increase a resistance of the memory cell that is in the target resistance state, the post-write pulse being applied as a single pulse having at least n stepped voltage levels, n being an integer equal to or more than 2, and an n-th stepped voltage level of the post-write pulse is set to be lower than a minimum threshold voltage level of the target resistance state that is changed by an (n&#x2212;1)-th stepped voltage level of the post-write pulse.

Method of operating resistive memory device to increase read margin

A variable resistance memory device includes a word line extending in a first direction, a bit line on the word line and extending in a second direction intersecting the first direction, a switching pattern between the bit line and the word line, a phase change pattern between the switching pattern and the word line, and a bottom electrode between the phase change pattern and the word line, wherein the phase change pattern has a bottom area greater than a top area of the bottom electrode, a thickness of the phase change pattern being greater than a thickness of the bottom electrode, and wherein the bottom and top areas are defined in the first and second directions, and the thicknesses are defined in a third direction intersecting the first and second directions.

Variable resistance memory device

The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.

Semiconductor devices and methods of manufacturing the same

The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.

A method of manufacturing a semiconductor device includes forming a first gate structure on a substrate, the first gate structure including a gate insulation layer, a gate electrode, and a hard mask sequentially stacked on the substrate, forming a preliminary spacer layer on sidewalls of the first gate structure and the substrate, the preliminary spacer layer including silicon nitride, implanting molecular ions into the preliminary spacer layer to form a spacer layer having a dielectric constant lower than a dielectric constant of the preliminary spacer layer, anisotropically etching the spacer layer to form spacers on the sidewalls of the first gate structure, and forming impurity regions at upper portions of the substrate adjacent to the first gate structure.

Methods of manufacturing a semiconductor device

A method of authenticating a user of an image forming apparatus is provided that includes receiving, at the image forming apparatus, a one-time password (OTP) generating request, generating, at the image forming apparatus, an OTP according to the OTP generating request, receiving, at the image forming apparatus, an authentication request, from the host apparatus, including the OTP, and when the OTP received from the host apparatus matches the OTP generated according to the OTP generating request and absent a condition, approving an access to the image forming apparatus.

Image forming apparatus and method of authenticating user thereof

A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance value of the memory cell on the target time using the resistance drift coefficient; and determining whether the resistance value calculated satisfies the target resistance value.

Resistive nonvolatile memory device having cells programmed to achieve a target resistance value at a target time and writing method thereof

A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

Method of refreshing volatile memory device

A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a lower row address of an input refresh leveraging address corresponding to the decided refresh leveraging row driving unit to a don't care state; and internally generating the don't care lower row address of the refresh leveraging address to drive word lines according to a combined refresh leveraging address.

Semiconductor memory device and refresh leveraging driving method thereof

Memory devices include a row decoder, a first variable resistance memory cell connected to a first bit line and connected to the row decoder by a word line and a second variable resistance memory cell connected to a second bit line and connected to the row decoder by the word line. The memory devices further include a bit line select circuit coupled to the first and second bit lines and configured to compensate for a difference in word line resistance between the row decoder and the respective first and second memory cells. In some embodiments, the bit line select circuit includes first and second transistors configured to selective respective ones of the first and second bit lines and the first and second transistors have different resistances that compensate for the difference in word line resistance.

Variable resistance memory devices compensating for word line resistance

A variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.

Resistive memory device capable of compensating for variations of bit line resistances

An integrated circuit memory cell includes a substrate having a first semiconductor region of first conductivity type (e.g., N-type) therein, which may define a portion of a word line within the substrate. An electrically insulating layer is provided on the substrate. The electrically insulating layer has an opening therein that extends opposite a recess in the first semiconductor region. A first insulating spacer is provided on a sidewall of the recess in the first semiconductor region. A diode is provided in the opening. The diode has a first terminal electrically coupled to a bottom of the recess in the first semiconductor region. A variable resistivity material region (e.g., phase-changeable material region) is also provided. The variable resistivity material region is electrically coupled to a second terminal of the diode.

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Hwaseong-si, South Korea

Kwang-woo Lee