Samsung Electronics Co., Ltd.

Kwang-Won Park

Chang-Hyun Lee

Jeong-Ho Park

Byoung-sul Kim

Jun-Ho Jo

Jung-in Han

Hyun-Chul Shin

Hak-Yong Lee

Jung-Young Lee

Provided are a semiconductor package, a semiconductor memory module including the semiconductor package, and a system including the semiconductor memory module. The semiconductor package may include a plurality of main terminals arranged on a surface of the semiconductor package with constant intervals, and the plurality of main terminals may include terminals of a first set including a plurality of input/output terminals to which test signals may be input, and terminals of a second set including a plurality of input/output terminals to/from which signals other than the test signals may be input/output.

Semiconductor packages

A non-volatile memory device having a hidden cell located separate from data storage cells, and a method of effectively managing an erase count of the non-volatile memory device. The method includes preparing the non-volatile memory device that includes a hidden cell located separate from data storage cells and is not accessible to users of the data storage cells, and increasing an erase count stored in an erase count storing region of the hidden cell corresponding to at least one erased data storage cell when the at least one data storage cell is erased.

Method and apparatus for managing erase count of memory device

Intermediate structures are provided that are formed during the manufacture of a memory device. These structures include first and second spaced apart gate patterns on a semiconductor substrate. A source/drain region is provided in the semiconductor substrate between the first and second gate patterns. An etch stop layer is provided on first and second sidewalls of the first gate pattern. The first and second sidewalls face each other to define a gap region between the etch stop layer on the first sidewall and the etch stop layer on the second sidewall. A dielectric layer is provided in the gap region. Finally, a preliminary contact hole is provided in the dielectric layer.

Intermediate structures having reduced width contact holes that are formed during manufacture of memory cells having contact structures

Methods of forming a cell of a NOR-type flash memory device are provided in which a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall are formed on a semiconductor substrate. A source/drain region is formed in the semiconductor substrate between the first and second gate patterns. An etch stop layer is formed on the first and second sidewalls that defines a gap region. A dielectric layer is formed in the gap region, and is then etched to form a contact hole. Finally, a conductive material is deposited in the contact hole.

Methods of forming contact structures for memory cells using both anisotropic and isotropic etching

Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage. A third erasure voltage is applied to a first inner dummy control gate electrode adjacent to the first outermost main control gate electrode and a second inner dummy control gate electrode adjacent to the second outermost main control gate electrode. The third erasure voltage is less than the second erasure voltage. Related devices are also provided.

Growing community of inventors

Gyeonggi-do, South Korea

Kwang-Won Park