Skhynix Inc.

Other

Nanobrick Co., Ltd.

Kwang Su Kim

Youn Won Park

Seok Lee

Jae Hyun Joo

Da Hyeon Go

Sung Wan Hong

Embodiments of the present disclosure relate to a memory system and an operating method thereof. The memory system may include a first processor and a second processor. The first processor is configured to manage or process a main read count table including a plurality of first read count table entries each corresponding to one of a plurality of super memory blocks. The second processor is configured to manage or process, when an error occurs during an operation of reading data stored in one of the plurality of super memory blocks, a partial read count table including a read count table entry including information on a count of the read operation executed during a recovery operation for the error, and transmit an update message to the first processor for updating the main read count table based on the partial read count table.

Memory system and operating method thereof

Provided herein may be a storage device and a method of operating the same. The method of operating a storage device including a replay protected memory block (RPMB) may include receiving a write request for the RPMB from an external host, selectively storing data in the RPMB based on an authentication operation, receiving a read request from the external host, and providing result data to the external host in response to the read request, wherein the read request includes a message indicating that a read command to be subsequently received from the external host is a command related to the result data.

Memory controller for RPMB-inclusive memory device, operating method thereof and electronic device including the same

A memory system may include a storage device and a memory controller. The storage device may include a plurality of memory blocks. Each of the memory blocks may include a plurality of pages. The memory controller may perform a maintenance management operation including predetermined numbers of sub-operations performed for a first period in each first cycle on the storage device, wherein the memory controller is configured to increase a reservation number of the sub-operations when a first type command requested from an external device is processed at a time of triggering the sub-operations, and determine a trigger interval of the sub-operations based on the reservation number.

Memory system with secured performance and reliability, memory controller and method of operating the same

A memory system, a memory controller and an operating method are disclosed. A first area, a second area included in the first area, and a third area are set. An area to which target data is to be written is determined to the first area or the third area. When the target data is written to the first area, the target data is preferentially written to the second area. The number of data bits stored per memory cell in the first area is less than the number of data bits stored per memory cell in the third area. As a consequence, it is possible to secure storage capacity of the memory system to at least a set reference while securing data write performance of the memory system recognized by a host to at least a set reference.

Memory system, memory controller and operating method

A memory system may include: a nonvolatile memory device suitable for storing user data and meta data of the user data; and a controller suitable for uploading at least some of the meta data to a host. When the size of a free space of a storage space of the host, allocated to store the uploaded meta data, is equal to or less than a preset value, the controller may upload hot meta data to the host according to the number of normal read requests received from the host and the ratio of the normal read requests.

Memory system uploading hot metadata to a host based on free space size of a host memory, and read operation method thereof

The present disclosure relates to an electronic device. According to the present disclosure, a storage device includes a memory controller acquiring a valid address reflecting a bad block more quickly and a plurality of memory devices each including a plurality of memory blocks included in each of a plurality of planes.

Storage device and operating method thereof

Storage device and method of operating the same

An electronic device includes a memory controller selecting map data to be output to a host. The memory controller includes an address counter and a map data selector. The address counter counts a number of times a logical block address corresponding to a request is received based on the request received from the host and outputs an activation signal indicating that an index to which the logical block address belongs is an activation index when an activation count corresponding to the index is equal to or greater than a preset value, the activation count being generated based on a counting result. The map data selector selects map data to be output to the host based on the activation signal. The address counter decreases the activation count by a preset size when a size of the selected map data exceeds a storage capacity of the host allocated for storing map data.

Memory controller performing host-aware performance booster mode and method of operating the same

Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command.

Memory system and method of operating the same

A memory system includes: a first memory subsystem suitable for storing a first segment of map data for first logical addresses in a logical address region; a second memory subsystem suitable for storing a second segment of map data for second logical addresses in the logical address region; and a host interface suitable for: providing any one of the first and second memory subsystems with a first read command of a host according to a logical address included in the read command, providing the host with an activation recommendation according to a read count of the logical address region including the provided logical address, providing map data for the first and second logical addresses obtained from the first and second memory subsystems, wherein the activation recommendation allows the host to further provide a physical address corresponding to a target logical address in the logical address region.

Controller, memory system and data processing system

A memory system, a memory controller, and an operating method therefor. The memory system includes a first processor configured to determine a processor, among multiple processor including the first processor, to process read operations on logical addresses indicated by read commands, and process a write operation on a logical address indicated by a write command; and a second processor, among the multiple processors, configured to process a read operation on a target logical address selected by the first processor among the logical addresses. The first processor searches for mapping information on a logical address corresponding to a read or write operation to be processed by the first processor, by using a first map search engine, and the second processor searches for mapping information on the target logical address by using a second map search engine. It is possible to improve the performance of searching for mapping information in a read operation.

Memory system, memory controller and method for operating memory system in which different processors search for mapping information using different map search engines

Provided herein may be a memory controller and a method of operating the same. The memory controller may control a write operation of a memory device in response to a write command received from a host. The memory controller includes a host interface, a buffer, and a first processor. The host interface is configured to receive write data corresponding to the write command from the host. The buffer is configured to store the write data. The first processor is configured to control operations of the host interface and the buffer. The first processor is configured to, when the write command is received, set an operation mode based on an operating status of the memory controller.

Growing community of inventors

Gyeonggi-do, South Korea

Kwang Su Kim