Samsung Electronics Co., Ltd.

Kwang Soo Seol

Sunghoi Hur

Seong Soon Cho

Jungdal Choi

Jintae Kang

Youngwoo Park

Kihyun Hwang

Kwangmin Park

Hanmei Choi

Chanjin Park

Juyul Lee

Toshiro Nakanishi

Wansik Hwang

Taekyung Kim

Jae Young Choi

Kyoung Lae Cho

Jang-Gn Yun

Seong Jae Choi

Jaeduk Lee

Jaegoo Lee

SeungHyun Lim

Dae Sin Kim

Byungkwan You

Homin Son

Daewoong Kang

Byungkyu Cho

Sunil Shim

Changhyun Lee

Jaehoon Jang

Byoungkeun Son

Sung-Il Chang

Dong Kee Yi

Yoondong Park

Albert Fayrushin

Sung Ii Park

Jeonghyuk Choi

Kohji Kanamori

Jintaek Park

Deok-kee Kim

Sung-Il Park

Byoung Lyong Choi

Jin-Soo Lim

Jaehun Jung

Seon Mi Yoon

Dongchul Yoo

In-sung Joe

Hongsoo Kim

Dohyun Lee

In Sung Joe

Zhiliang Xia

Sukpil Kim

Janggn Yun

Hyun-Wook Lee

Hyunchul Back

Byungjoo Go

Changsub Lee

Nambin Kim

Kim Taekyung

Byoung Ho Cheong

A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Semiconductor device, systems and methods of manufacture

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Three-dimensional semiconductor memory devices and methods of fabricating the same

Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.

Semiconductor device

A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.

Non-volatile memory devices including charge storage layers

A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.

Vertical memory devices having charge storage layers with thinned portions

A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower select gate line of the non-volatile memory device.

Non-volatile memory devices including vertical NAND channels and methods of forming the same

A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.

Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

Memory device

Growing community of inventors

Yongin-si, South Korea

Kwang Soo Seol