Samsung Electronics Co., Ltd.

Samsung Electro-Mechanics Co., Ltd.

Rensselaer Polytechnic Institute

Kwang-Soo Park

Jae-jun Lee

Jong-hoon Kim

Kyu-Hyoun Kim

Joo-sun Choi

Ji-woon Park

Young-chan Jang

Dae-Jung Byun

Hoe-Ju Chung

Young Nam Yun

Byung-Se So

Jung-Joon Lee

Su-jin Kim

Jeong-Hyeon Cho

Kwang-Seop Kim

Jung-Hee Cho

Jin-ho So

Byung-Ho Kim

Byoung-Ha Oh

Bong-Soo Kim

Moon-Jung Kim

Sun-ki Yun

Myung-Gun Chong

Yong-Ho Ko

Hyun-ae Lee

Sim-Hwan Park

Kyung-suk Kim

Jeong-Yeon Jeong

Dong-Sam You

A data storage device is provided. The data store device includes a first printed circuit board (PCB) comprising a main transmission line formed on at least one surface of the first PCB and/or within the first PCB, a memory controller and a plurality of nonvolatile memory devices. The memory controller is provided on the first PCB. The plurality of nonvolatile memory devices are provided on the first PCB. The plurality of nonvolatile memory devices are connected to the memory controller through a channel and exchange data with the memory controller. The channel includes a data transmission line connecting data pads of the memory controller and the nonvolatile memory devices. The data transmission line comprises the main transmission pattern and an open stub contacting the main transmission pattern. The open stub does not contact any other conductor other than the main transmission pattern.

Data storage device including transmission line having open stub and method of operating the same

A memory module includes at least two rows of memory device packages on a substrate and coupled to a control signal line. A first memory device package in a first row is connected to the control signal line at a first point closest to the proximal end of the control signal line and a second memory device in a second row is connected to the control signal line at a second point next closest to the first point. A signal trace length between the first memory device and the second memory device may be greater than a signal trace length between the first memory device package and a third memory device package immediately adjacent the first memory device package in the first row or a signal trace length between the second memory device package and a fourth memory device package immediately adjacent the second memory device package in the second row.

Buffer memory devices, memory modules and solid state disks with non-uniform memory device connections

A storage controller includes a first on-die termination (ODT) circuit, a second ODT circuit and an ODT control circuit. The first ODT circuit provides a first termination resistance with a strobe signal line transferring a data strobe signal. The second ODT circuit provides a second termination resistance with at least one data line transferring data. The ODT control circuit individually controls activation and deactivation of the first ODT circuit and the second ODT circuit.

Storage controllers, methods of operating the same and solid state disks including the same

A memory system having improved signal integrity includes a printed circuit board for use in a memory device, N memory semiconductor packages mounted on the printed circuit board, a first switch mounted on the printed circuit board, a controller mounted on the printed circuit board, N first signal lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to-1 correspondence, a second signal line connecting the first switch to the controller, and N selection lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to-1 correspondence. The N selection lines connect the semiconductor packages to the controller and transmit an enable signal. N is a natural number.

Memory system having improved signal integrity

A memory system includes a controller having first and second input/output terminals, and first and second memory devices each having first and second input/output terminals. The system includes a path selection mechanism for selectively employing one of the first and second terminals of either the controller or the first memory device for communicating a first input/output signal between the controller and the first memory device, and employing the other one of the first and second terminals for communicating a second input/output signal between the controller and the first memory device. The path selection mechanism selectively employs the first and second terminals in accordance with data indicating which of the first and second terminals of the first memory device is connected to the first terminal of the controller and which of the first and second terminals of the first memory device is connected to the second terminal of the controller.

Memory system supporting input/output path swap

An apparatus capable of selectively applying different types of connectors to a substrate is disclosed. The memory apparatus includes a substrate having a controller. First and second connector pads may be arranged on edges of top and bottom surfaces of the substrate. A via hole may be arranged between the controller and the first and second connector pads. A first passive device pad may be arranged between the via hole and the first connector pads. A second passive device pad may be arranged between the via hole and the second connector pads. A passive device may be coupled to only one of the first passive device pad or the second passive device pad.

Apparatus capable of selectively using different types of connectors

A device to selectively activate memory chips includes a memory unit including n memory chips activated in response to n memory chip activation signals (n is a natural number), a controller to generate m control signals (m is a natural number), and a memory chip activation signal generator to combine m chip enable (CE) signals to generate the n memory chip activation signals.

Data storage device

A printed circuit board (PCB) includes a substrate having a first group of at least two via holes and a second group of at least two via holes formed therein, a first pad set of terminal pads and a second pad set of terminal pads formed on the substrate, and a first group of conductive connection members and a second group of conductive connection members formed in the substrate. The first group of the via holes are surrounded by the first pad set of the terminal pads and the second group of the via holes are surrounded by the second pad set of the terminal pads. The first and the second groups of conductive connection members fill up the first and second groups of the via holes. The first group of the conductive connection members are connected to the first pad set of the terminal pads and the second group of the conductive connection members are connected to the second pad set of the terminal pads.

Printed circuit board and semiconductor module having the same

A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding one of the at least one termination resistors. A control signal generator generates a control signal for selectively enabling the termination circuit by controlling each of the at least one switches. The control signal has an input period less than or equal to an input period of a data signal.

Termination circuits and semiconductor memory devices having the same

Data transmission system and method are provided. The transmission system includes a data converter and data restoring unit. The data converter converts N-bit first data to be transmitted into M-bit second data, where M is greater than N and the second data is arranged in a minimum unit greater than 1, each minimum unit including at least successive data bits having the same phase. The transmitter compresses the second data prior to transmission via a channel having performance characteristics defining a minimum pulse width, and a receiver receives and de-compresses the transmitted second data. The data restoring unit then restores the first data from the second.

Data transmission system and method

A printed circuit board, a method of manufacturing the printed circuit board, and an apparatus for perforating via holes are disclosed. By use of a method of manufacturing a printed circuit board that includes forming a first circuit pattern, which includes a reference mark and a via land, on one surface of an insulation substrate; stacking a metal layer on the insulation layer; opening a first window in the metal layer in correspondence with the reference mark; and forming a via which electrically connects the via land with the metal layer, by irradiating light towards the other surface of the insulation substrate and identifying the reference mark through the first window, the occurrence of short-circuiting is prevented in forming vias for electrical interconnection between circuit patterns in a printed circuit board, and as the defect rate caused by eccentricity between insulation layers may be reduced, aspects of the invention may contribute to reducing costs.

Printed circuit board, method of manufacturing the same, and apparatus for perforating via holes

A substrate includes a power plane and a ground plane that are placed apart from and are substantially parallel to each other, and at least one signal line that is placed between the power plane and the ground plane. The ground plane includes a first conductive layer having a first conductivity. The power plane includes a second conductive layer having the first conductivity, and the power plane or the ground plane includes a third conductive layer having a second conductivity lower than the first conductivity. The third conductive layer faces the at least one signal line across a dielectric substance.

Substrate having a structure for suppressing noise generated in a power plane and/or a ground plane, and an electronic system including the same

A probe card to connect a semiconductor device to test equipment includes a Printed Circuit Board (PCB) in which an electrical wiring pattern is formed, a first connector fixed on an upper surface of the PCB to connect the test equipment to the PCB, probe needles connected to electrode pads of the semiconductor device, and a Flexible PCB (FPCB) to connect the PCB to the probe needles. Accordingly, a signal transmission characteristic can be enhanced, test expenses can be reduced, and ground noise can be reduced.

Probe card including a sub-plate with a main supporter and a sub-supporter with the sub-supporter having probe needles

Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.

Growing community of inventors

Suwon-si, South Korea

Kwang-Soo Park