Samsung Electronics Co., Ltd.

Postech Academy-Industry Foundation

Kwang-soo Kim

Junhyoung Kim

Byeong-hwan Jeon

Kohji Kanamori

Jae-Hoon Jang

Jin-Won Kim

Geunwon Lim

Sang-Cheol Park

Wook-rae Kim

Tae-joong Kim

Yong-Seok Kim

Ken Ozawa

Tae-hun Kim

Sun-Il Shim

Jisung Cheon

Kyong-Ha Park

Hee Cheul Jung

Tae-Seok Jang

Hyun-Suk Min

Bonghyun Choi

Siwan Kim

Hae-min Lee

Min-kyung Bae

Yu-sin Yang

Chung-sam Jun

Jae-Duk Lee

Sang-kil Lee

Seokcheon Baek

Sung-Won Park

Sang-Pil Sim

Do-sung Jung

Shin-Hwan Kang

Sang-Jun Lee

Harutaka Sekiya

In-jae Lee

Mitsunori Numata

Chan-Kwang Park

Young-kyu Park

Jeong-Gwan Kang

Akio Ishikawa

Heonkyu Lee

Ji-hoon Kang

Yong-Deok Jeong

Byoung-Chul Ko

Young-duk Kim

Heon-Kyu Lee

Se Mee Jang

Sean Park

Heon-kyu Lee

Hyong-Woo Yu

Kwang-jun Yoon

Heon-ju Shin

Myung-jun Lee

Jee-Hoon Ka

Gwang-sik Park

Se-Young Oh

Sam-Yong Kim

Young-Woo Ryu

Hee-Seob Ryu

Disclosed is a semiconductor package comprising a substrate that includes a plurality of substrate pads on a top surface of the substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip, and a plurality of first bonding wires on a top surface of the first semiconductor chip and coupled to the substrate pads. The first semiconductor chip includes a first lower signal pad, a second lower signal pad laterally spaced apart from the first lower signal pad, and a lower signal redistribution pattern electrically connected to the first lower signal pad and the second lower signal pad. One of the first bonding wires is coupled to the first lower signal pad. Any of the first bonding wires is not on a top surface of the second lower signal pad.

Semiconductor package

A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

Semiconductor memory device

A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

Three-dimensional semiconductor memory device

A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

A vertical semiconductor device includes odd and even cell blocks, and odd and even block pad structures. Each of the odd cell blocks includes first conductive line structures including conductive lines and insulation layers alternatively stacked in a first direction. Each of the even cell blocks includes second conductive line structures having substantially the same shape as the first conductive line structures. The odd block pad structure is connected to first edge portions of the first conductive line structures. The even block pad structure is connected to second edge portions, opposite the first edge portions, of the second conductive line structures. Each of the odd cell blocks and the even cell blocks has a first width in a third direction. Each of the odd and even block pad structures is formed on a region of a substrate having a second width greater than the first width in the third direction.

Vertical semiconductor devices

An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

Vertical memory device including common source line structure

Systems and methods related to a structured illumination (SI)-based inspection apparatus are described. The SI-based inspection apparatus may be capable of accurately inspecting an inspection object in real time with high resolution, while reducing the loss of light. Also described are an inspection method, and a semiconductor device fabrication method including the SI-based inspection method. The inspection apparatus may include a light source configured to generate and output a light beam, a phase shifting grating (PSG) configured to convert the light beam from the light source into the SI, a beam splitter configured to cause the SI to be incident on an inspection object and output a reflected beam from the inspection object, a stage capable of moving the inspection object and on which the inspection object is arranged, and a time-delayed integration (TDI) camera configured to capture images of the inspection object by detecting the reflected beam.

Structured illumination-based inspection apparatus and inspection method, and semiconductor device fabrication method including structured illumination-based inspection method

A three-dimensional semiconductor memory device includes a plurality of first insulating layers vertically stacked on a peripheral logic structure, second insulating layers stacked alternately with the first insulating layers, conductive layers stacked alternately with the first insulating layers and disposed on sidewalls of the second insulating layers, through-interconnections penetrating the first insulating layers and the second insulating layers so as to be connected to the peripheral logic structure, and a first conductive line electrically connected to a plurality of first conductive layers of the conductive layers.

Three-dimensional semiconductor memory devices

A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.

Semiconductor device including vertical channel layer

Three-dimensional semiconductor memory devices are provided. The devices may include a semiconductor layer and electrode structures on the semiconductor layer. The electrode structures may include a first electrode structure including a first electrode portion and a first pad portion and a second electrode structure including a second electrode portion and a second pad portion. Each of the first and second electrode portions has a first width, each of the first and second pad portions has a second width, and the second width may be less than the first width. The first and second electrode portions may be spaced apart from each other by a first distance, and the first and second pad portions may be spaced apart from each other by a second distance that may be greater than the first distance.

An imaging apparatus includes an illumination light source to output an illumination light, an illumination optical system to transmit the illumination light toward a sample, an imaging optical system to transmit light reflected from the sample, a stage to move the sample in a predetermined transfer direction, and a photographing unit to receive the reflected light. The imaging apparatus may include one or more diffraction grids located at conjugate focal planes of the sample. The operation of the photographing unit may be synchronized with a movement of the sample by the stage to obtain an image in accordance with a time delay integration method.

Imaging apparatus and imaging method

Growing community of inventors

Hwaseong-si, South Korea

Kwang-soo Kim