Hyundai Electronics Industries Co. Ltd.

Kwang-Myoung Rho

Chan-Kwang Park

Yo-Hwan Koh

Seong-Min Hwang

A method of manufacturing a semiconductor device, capable of securing an alignment margin between bit lines and a storage node contact is disclosed herein. The method includes: a depositing step of a first insulating layer on a semiconductor substrate of MOS structure; a forming step of a bit line pattern; a depositing step of a second insulating layer; a depositing step of sequentially a third and fourth insulating layers which have different etch rates; a masking and etching step of said fourth and third insulating layers to form T-shaped patterns in cross-sectional view; a forming step of polysilicon spacers at sidewalls of the T-shaped insulating patterns; a depositing step of a fifth insulating layer; a forming step of first photoresist mask pattern; etching steps of etching a predetermined portion of the fifth insulating layer, etching the T-shaped insulating layer pattern, etching the second insulating layer, etching the bit line pattern and etching the first insulating layer; a forming step of bit line contact; a depositing step of a sixth insulating layer; a forming step of second photoresist mask pattern for forming storage node contact hole on the sixth insulating layer and a forming step of a storage node contact hole by etching the predetermined portions of the sixth and fifth insulating layers, the T-shaped pattern, and the second and first insulating layer, sequentially.

Growing community of inventors

Seoul, South Korea

Kwang-Myoung Rho