Samsung Electronics Co., Ltd.

Kwang-Myeong Jang

Han-gu Sohn

Jin-hyoung Kwon

Ho-Cheol Lee

Kyung-Woo Nam

A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.

Multi port memory device with shared memory area using latch type memory cells and driving method

A multiport semiconductor memory device having a processor wake-up function and multiprocessor system, the multiprocessor system including a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first and second processors. The multiport semiconductor memory device includes a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator. The first processor is coupled to the at least one shared memory area via the first port, the second processor is coupled to the at least one shared memory area via the second port, and the wake-up signal generator is coupled to the first processor and the second processor.

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Hwaseong-si, South Korea

Kwang-Myeong Jang