Samsung Electronics Co., Ltd.

Kwang Min Park

Jae Ho Jung

Jae Ho Choi

Seung Hyun Lim

Bio Kim

Zhe Wu

Jae Young Ahn

Jeon Il Lee

Ja Bin Lee

Young Jin Noh

Jong Uk Kim

Dong Chul Yoo

Dong Sung Choi

A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.

Semiconductor memory device with selection patterns, storage patterns, and a gap fill layer and method for fabricating the same

A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.

Semiconductor device with a tunneling layer having a varying nitrogen concentration, and method of manufacturing the same

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Kwang Min Park