Samsung Electronics Co., Ltd.

Kwang-Min Park

Jae-young Ahn

Young-jin Noh

Hun-hyeong Lim

Ju-Mi Yun

Ki-Hyun Hwang

Dong-Chul Yoo

Jeon-Il Lee

Guk-Hyon Yon

Joong-Yun Ra

Young-Seon Son

Chang-Hyun Lee

Si-Young Choi

Jae-Ho Choi

Han-Mei Choi

Seung-hwan Lee

Ji-Hoon Choi

Jeong-Hee Park

Hong-suk Kim

Seung-Jae Baik

Jong-Uk Kim

Young-Min Ko

Ki-hyun Hwang

Sung-Kweon Baek

Sun-jung Kim

Bi-O Kim

Sung-hae Lee

Byong-Ju Kim

In-Sun Yi

Eun-sung Seo

Eun-Yeoung Choi

Young-chang Song

Dong-Sung Choi

A variable resistance memory device may include a memory unit including a first electrode disposed on a substrate, a variable resistance pattern disposed on the first electrode and a second electrode disposed on the variable resistance pattern, a selection pattern disposed on the memory unit, and a capping structure covering a sidewall of the selection pattern. The capping structure may include a first capping pattern and a second capping pattern sequentially stacked on at least one sidewall of the selection pattern. The first capping pattern may be silicon pattern, and the second capping pattern may include a nitride.

Variable resistance memory device including silicon capping pattern

A substrate processing apparatus including a process chamber configured to receive a plurality of substrates oriented in a horizontal manner and vertically arranged with respect to the process chamber, a process gas supply unit configured to supply at least one process gas to the process chamber through a process gas supply nozzle, the process gas supply nozzle along an inner wall of the process chamber in a direction in which the substrates are sacked, an exhaust unit configured to exhaust the process gas from the process chamber, and a blocking gas supply unit configured to supply a blocking gas through a blocking gas injector provided in a circumferential direction of the process chamber such that a flow of the process gas in the process chamber is controlled may be provided.

Substrate processing apparatus

A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Semiconductor devices and methods of manufacturing the same

Non-volatile semiconductor devices

Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.

Tunnel insulation layer structures, methods of manufacturing the same, and vertical memory devices including the same

In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

Method of manufacturing a non-volatile memory device

Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation film. The blocking insulation film includes a stacked film structure of a high-dielectric film and a barrier insulation film. The high-dielectric film has a first potential barrier relative to the charge-trapping layer. The barrier insulation film has a second potential barrier relative to the charge-trapping layer which is higher than the first potential barrier. The blocking insulation film has a thickness in a range of about 5 &#x212b; to about 15 &#x212b;.

Non-volatile semiconductor memory devices and methods of fabricating the same

Growing community of inventors

Seoul, South Korea

Kwang-Min Park