Skhynix Inc.

Kwang Min Lim

Hee Youl Lee

Tae Un Youn

Hye Lyoung Lee

A semiconductor memory device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory blocks coupled to a common source line. The peripheral circuit performs a program operation on a memory block selected from among the memory blocks. The control logic controls the program operation of the peripheral circuit. The memory blocks are coupled to corresponding source select lines, respectively. The program operation includes a plurality of program loops, each including a channel precharge operation. During the channel precharge operation, the control logic controls the peripheral circuit so that the common source line floats and a voltage of a source select line coupled to an unselected memory block, among the memory blocks, is increased.

Semiconductor memory device performing program operation and method of operating the same

A semiconductor memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes dummy memory cells connected to dummy word lines and normal memory cells connected to normal word lines. The peripheral circuit performs an erase operation on the memory block. The control logic controls an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a pre-program operation on first dummy memory cells connected to first dummy word lines among the dummy word lines, in response to an erase command for the memory block, and perform a pre-program operation on second dummy memory cells connected to second dummy word lines among the dummy word lines, after the pre-program operation on the first dummy memory cells. The control logic controls the peripheral circuit to perform an erase operation on the normal memory cells.

Semiconductor memory device and operating method thereof

The present technology relates to a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells corresponding to a plurality of word line groups, a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation, a voltage generation circuit configured to apply an operation voltage increasing from a first operation voltage to a second operation voltage to the plurality of word line groups during the erase operation, and a control logic configured to control the source line driver and the voltage generation circuit to perform a suspend operation of stopping the erase operation.

Memory device and method of operating the memory device

Semiconductor memory device and method of operating the same whereby the voltage of a floated common source line is increased by increasing the voltage of a source select line coupled to an unselected memory block

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Icheon-si Gyeonggi-do, South Korea

Kwang Min Lim