Samsung Electronics Co., Ltd.

Kwang-Kyu Bang

Young-Min Kim

Kyeong-seon Shin

Ho-jeong Choi

Kwan-Bin Yim

Kwan-Jong Park

Sang-Gil Kim

Myoung-Sub Kim

Hyun-Soo Kim

Yusuf Cinar

Jeong-Ho Bang

Hwi-jong Yoo

Ho-Jeong Choi

Hyen-wook Ju

Kun-gu Lee

Yong-won Lee

Jeong-kyu Kim

Min-gwon Moon

Seung-Gyoo Choi

Il-do Seo

Yu-hyun Oh

Kyoung-Suk Lyu

Provided is a storage device including a power management integrated circuit chip; multiple non-volatile memories configured to receive power from the power management integrated circuit chip; and a controller configured to control the non-volatile memories, wherein the controller checks a state of the power during a read operation and a write operation on the non-volatile memories and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories.

Storage device and storage system

A memory module includes a module board extending in one direction, a plurality of electronic elements mounted on the module board, and at least one stress detection pattern in a position between the electronic elements or adjacent to one or more of the electronic elements on the module board and including a plurality of strips configured to indicate a stress level generated in the position by an external force applied to the module board.

Memory module and solid state drive having the same

A storage device test system includes: a storage device mounting unit configured to mount a storage device therein; a test control unit configured to transmit and/or receive test signals to and/or from the storage device; an interface plug that is electrically connected to the test control unit and coupled to the storage device mounted in the storage device mounting unit; and a plugging driving unit that controls a relative location between the interface plug and the storage device mounting unit. By using the storage device test system, the causes of defects that may occur while using a storage device may be easily detected.

Storage device test system

Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test terminals, which may permit in situ testing of one or more components of the solid state device products.

Solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same

According to example embodiments, a solid state drive system includes at least one semiconductor memory, a control circuit including first connection terminals, and second connection terminals. The first connection terminals may be configured to supply one or more operational voltages to the at least one semiconductor memory. The second connection terminals may be configured to supply one or more test voltages to the at least one semiconductor memory.

Solid state drive systems and methods of reducing test times of the same

A fuse box of a semiconductor memory device which comprises a plurality of fuse units commonly connected to a power line, each of the fuse units comprising a first fuse connected with the power line; and a plurality of second fuses connected with the first fuse in parallel. If the second fuses are determined to be cut off, the first fuse is cut off instead of the second fuses.

Fuse box and semiconductor memory device including the same

Provided are a semiconductor device including a fuse focus detector, a fabrication method thereof and a laser repair method. In a chip region, fuses may be formed at a first level. A fuse focus detector including first and second conductive layers may be formed in a scribe line region. The first conductive layer may be formed at the first level, while the second conductive layer may be formed at a different level. For a laser repair method, a target region may be divided into sub-regions. In one selected sub-region, the fuse focus detector may be laser scanned in a direction for a reflection light measurement providing information on a thickness of the fuse focus detector. Using the thickness information, a focus offset value of a fuse in the selected sub-region may be calculated. When the focus offset value is within an allowable range, fuse cutting may be performed.

Semiconductor device including fuse focus detector, fabricating method thereof and laser repair method using the fuse focus detector

A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.

Fuse regions of a semiconductor memory device and methods of fabricating the same

The invention relates to a fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one example of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit includes a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.

Architecture of laser fuse box of semiconductor integrated circuit and method for fabricating the same

A fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one embodiment of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit comprises a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.

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Hwaseong-si, South Korea

Kwang-Kyu Bang