Hynix Semiconductor Inc.

Skhynix Inc.

Snk Patent Law Offices

Kwang-Jin Na

Tae-Wook Kang

Hoon Moo Choi

Hae-Rang Choi

Kwan-Dong Kim

Seok-Bo Shim

Joo-Hwan Cho

A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.

Phase-locked loop and integrated circuit chip including the same, and test system including the integrated circuit chip

A noise detection circuit includes a first delay unit suitable for delaying a periodic wave to output a delayed periodic wave, a first divider unit suitable for dividing the delayed periodic wave to output a first periodic wave, a second divider unit suitable for dividing the periodic wave to output a divided periodic wave, a second delay unit suitable for delaying the divided periodic wave to output a second periodic wave, and a detection unit suitable for comparing the first periodic wave with the second periodic wave and outputting a noise detection signal.

Noise detection circuit, delay locked loop and duty cycle corrector including the same

A semiconductor device includes a first internal clock generation unit suitable for generating a first internal clock for synchronizing a first signal in response to a first external clock; a second internal clock generation unit suitable for generating a second internal clock for synchronizing a second signal in response to a second external clock; and a delay amount information provision unit suitable for providing delay amount information corresponding to a phase difference between the first internal clock and the second internal clock to an external device.

Semiconductor device and semiconductor system with the same

The DLL comprises a coarse delay line configured to have a plurality of unit delays and delay an reference dock to output a delayed clock, a fine delay line configured to delay the delayed clock to output a delayed output clock, a replica delay unit configured to delay the delayed output clock by an expected modeling value to output a feedback clock, a phase detection unit configured to compare a phase of the feedback clock with a phase of the reference clock to generate first to third phase detection signals based on a result of the comparison, a locking detection unit configured to output a locking signal by selecting a first locking detection signal or a second locking detection signal, and a control unit configured to control the coarse and fine delay lines in response to the locking signal and the first phase detection signal.

Delay locked loop circuit and method of driving the same

A semiconductor memory device includes a plurality of banks, a clock input unit configured to receive an external data clock, an internal data clock generation unit configured to receive the external data clock from the clock input unit and generate an internal data clock by delaying the external data clock by a delay amount which changes in correspondence to the number of banks activated among the plurality of banks, and a data buffer unit configured to buffer a data signal in response to the internal data clock.

Semiconductor memory device and method for operating the same

A duty cycle correction (DCC) circuit includes a duty signal generating unit configured to compare a high duration of an output clock with a low duration of the output clock in a clock cycle to generate a duty signal, a counting unit configured to count and output a preliminary code after a duty cycle correction (DCC) operation starts, a duty code generating unit configured to generate a duty code by selectively inverting or transferring without inversion the preliminary code in response to an initial value of the duty signal, and a duty cycle correcting unit configured to output the output clock by driving an input clock to a pull-up driving capacity and a pull-down driving capacity which are determined in response to the initial value of the duty signal and the duty code.

Duty cycle correction circuit

A semiconductor device includes an on-die termination circuit, a clock input unit, a clock phase mixing unit, and a data input/output unit. The on-die termination circuit is configured to calibrate a resistance of a termination pad and output an impedance matching code. The clock input unit is configured to receive a data clock. The clock phase mixing unit is configured to receive the data clock through the clock input unit and a delayed data clock, which is generated by delaying the data clock by a predetermined time, mix a phase of the data clock and a phase of the delayed data clock at a ratio corresponding to the impedance matching code, and output a phase-mixed data clock. The data input/output unit is configured to input/output a data signal in response to the phase-mixed data clock.

Clock delay correcting device and semiconductor device having the same

A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to synchronize a clock enable signal with each of the plurality of synchronization clock signals in an order beginning with a synchronization clock signal, on which a largest delay amount is reflected, to a synchronization clock signal, on which a smallest delay amount is reflected, and to generate a synchronized clock enable signal, and an internal clock generation section configured to generate an internal clock signal corresponding to the external clock signal, and to be on/off controlled in its operation in response to the synchronized clock enable signal.

Semiconductor device and method for operating the same

A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization signal. A delay control unit, when the initialization signal is enabled, transfers an initial voltage to be generated by dividing an external power supply voltage to a delay unit as a control voltage, and controls a delay operation of a delay reference clock to be selected on the basis of the clock selection signal.

DLL circuit and method of controlling the same

A semiconductor memory apparatus includes a clock input unit configured to receive a system clock and a data clock, a data clock phase regulation unit configured to regulate a frequency of the data clock, and delay the data clock by a delay varied in accordance with a training information signal, and a clock phase comparison unit configured to compare a phase of an output clock of the data clock phase regulation unit with a phase of the system clock, and generate the training information signal according to a result of the comparison.

Semiconductor memory apparatus and method for operating the same

A data output circuit in a semiconductor memory apparatus includes a first data driving unit configured to generate a first driving data at a first timing, a first buffering unit configured to generate a first output data by buffering the first driving data, a second data driving unit configured to generate a second driving data at a second timing that is different from the first timing, and a second buffering unit configured to generate a second output data by buffering the second driving data.

Data output circuit in semiconductor memory apparatus

A semiconductor memory device includes a delay locked loop (DLL) unit configured to generate a plurality of DLL clocks, each having a different phase according to delay values predefined by a DLL operation; a data output buffering unit configured to output data in response to the DLL clocks; and a skew compensating unit disposed between the DLL unit and the data output buffering unit to remove a clock skew occurring when the DLL clocks are transferred to the data output buffering unit.

Semiconductor memory device and method for driving the same

An apparatus for generating multi-phase clocks in accordance with the present invention includes a clock delay configured to delay a source clock by a delay time corresponding to a control signal to generate a plurality of clocks; a clock multiplexer configured to output a first clock for a first locking region and a second clock for a second locking region sequentially as a selected clock in response to a locking detection signal; a phase detector configured to detect a phase of the selected clock in comparison to a phase of the source clock to output a phase detection signal; and a control voltage signal generator configured to generate the control signal corresponding to the phase detection signal.

Apparatus and method for generating multi-phase clocks

There is provided an output driver of a semiconductor device in which a slew rate variance is small despite an environmental change and a slew rate can be easily controlled. The output driver includes a main driver for driving an output terminal, a delay unit for controlling a delay time of a driving control signal in response to a delay control signal, and a pre-driver for pre-driving an input terminal of the main driver in response to an output signal of the delay unit.

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Gyeonggi-do, South Korea

Kwang-Jin Na