Samsung Electronics Co., Ltd.

Kt Corporation

Hyundai Electronics Industries Co. Ltd.

Kwang-Jin Lee

Du-Eung Kim

Woo-Yeong Cho

Hye-Jin Kim

Beak-Hyung Cho

Qi Wang

Sang-beom Kang

Jun-Soo Bae

Kwang-Ho Kim

Joon-Min Park

Hye-jin Kim

Chang-Soo Lee

Choong-Keun Kwak

Hyung-Rok Oh

Nam-seog Kim

Won-Seok Lee

Su-Chang Jeon

Seong-hoon Woo

Hak-sun Kim

Uk-rae Cho

Hyun-Ho Choi

Yong-Jun Lee

Taek-Sung Kim

Jae-Yun Lee

Hui-kwon Seo

Dong-Hoon Jeong

Chang-soo Lee

Jong-Cheol Lee

Uk-Rae Cho

Mu-Hui Park

Yong-Jin Yoon

Joon-Yong Choi

Yong Seok Kwon

Yu-hwan Ro

Young-Kug Moon

Hui-Kwon Seo

Yong-Dae Park

Woo-Jung Sun

Mi-Kyoung Kang

Yu-Jin Huh

Hung-Jun An

Hwi-Jung Ryu

Sung-Ihk Yang

Sung-Kooc Lim

Byung-Gil Choi

Ki-sung Kim

Jung-Woo Park

Dae-Hwan Kang

Ji-Hyun Jeong

Dae-Won Ha

Young-Pil Kim

Hye Jin Kim

Hak-Soo Yu

Jong-Soo Seo

Yong Jun Lee

Gi-Tae Jeong

Jung Sunwoo

Hong-Sik Jeong

Tae-Hyoung Kim

Su-Chul Kim

Ki-Won Lim

Sang-Beom Kang

Hyun-Geun Byun

Du Eung Kim

Byong-Kwon Lee

Yu-Hwan Ro

Chang-han Choi

Young-Jae Son

Young-kug Moon

Jung-Hyuk Lee

Mu-hui Park

Kwon-Il Sohn

Joon Yong Choi

Ki-Chang Chun

Saeng-Hwan Kim

Byoung-Cheol Song

Sun Woo-Jung

A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Apparatus for outputting internal state of memory apparatus and memory system using the apparatus

A memory system is provided and includes memory chips and a memory controller. Each of the memory chips one or more first state output pins arranged therein. The memory controller has arranged therein a first state input pin connected in a wired-AND configuration to the one or more first state output pins arranged in the memory chips. The memory controller is configured to transmit a chip enable signal and/or an initially set function command to the memory chips. Each of the memory chips outputs a first state signal having one level from among three logic levels according to a first internal operation state of the memory chip to the one or more first state output pins of the memory chip based on the chip enable signal and/or the initially set function command.

A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact.

Memory devices having crosspoint memory arrays therein with multi-level word line and bit line structures

A nonvolatile memory module including a plurality of memory chips, a spare chip, and a module controller may be provided. The plurality of memory chips may be disposed on a printed circuit board (PCB), and each of the plurality of memory chips may include a plurality of nonvolatile memory cells. The spare chip may be disposed on the PCB and includes a plurality of nonvolatile memory cells. The spare chip may perform different functions according to operation modes of the plurality of memory chips. The module controller may disposed on the PCB, and control operations of the plurality of memory chips and the spare chip.

Nonvolatile memory modules and electronic devices having the same

The present disclosure is related to device management in a machine to machine (M2M) network. Particularly, the present disclosure relates to performing an efficient device management based on correlations between M2M devices in the M2M network.

Device management in machine to machine network

An apparatus for outputting an internal state of a memory apparatus and a memory system using the apparatus are provided. The apparatus includes a state signal generating circuit that generates a first signal indicating an internal operation state of the memory apparatus, and a state signal output control circuit that receives the first signal and outputs a second signal to an output pad based on a chip enable signal or an initially set function command, or both. The first signal indicates one state from among two states and the second signal indicates one state from among three states.

A memory system includes a nonvolatile memory module and a memory controller. The nonvolatile memory module includes a plurality of memory chips and a module controller disposed on a printed circuit board. The module controller controls operations of the plurality of memory chips. Each of the plurality of memory chips includes a plurality of nonvolatile memory cells and operates in an operation mode. The operation mode is either a memory mode or a storage mode. The memory controller performs a write operation and a read operation on the nonvolatile memory module, and performs a first error check and correction (ECC) operation on data communicated with the nonvolatile memory module. One of the module controller or the plurality of memory chips performs a second ECC operation on data stored in the plurality of memory chips based on the operation mode of the plurality of memory chips.

Memory systems and electronic devices including nonvolatile memory modules

The disclosure is related to managing a resource change in a machine to machine (M2M) network. Managing the resource change in M2M network by creating an abstract M2M entity object associated with a resource change, and creating an M2M entity object instance by embodying the abstract M2M entity object according to each application development environment.

Resource change management in machine to machine network

A nonvolatile memory module including a plurality of memory chips and a module controller on a printed circuit board (PCB) may be provided. Each of the plurality of memory chips may include a plurality of nonvolatile memory cell array layers stacked on a substrate in a three dimensional structure. The module controller may control operations of the plurality of memory chips. The module controller may operate each of the plurality of nonvolatile memory cell array layers included in each of the plurality of memory chips in one of a memory mode, in which a corresponding nonvolatile memory cell array layer is used as a working memory area that temporarily stores data for an operation of the nonvolatile memory module, and a storage mode, in which the corresponding nonvolatile memory cell array layer is used as a storage area that preserves data.

Nonvolatile memory devices including controller for operating nonvolatile memory cell array layer in memory chip in one of memory mode and storage mode

Provided is a driving method of a nonvolatile memory device for performing a write operation using a plurality of consecutive write loops. The driving method includes writing data to a plurality of nonvolatile memory cells during a first write loop, and after the first write loop, writing the data to the plurality of nonvolatile memory cells during a second write loop. A first maximum parallel bit size of the first write loop is n bits. A second maximum parallel bit size of the second write loop is m bits. m is greater than n.

Driving method of nonvolatile memory device using variable resistive element

Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.

Nonvolatile memory device with reduced coupling noise and driving method thereof

A method of operating a nonvolatile memory device comprises applying a read current with a first level to a nonvolatile memory cell comprising a variable resistance material, determining read data based on the applied read current, checking a syndrome corresponding to the read data to determine whether the read data is pass or fail, changing the read current from the first level to a second level, which is different from the first level, according to the determination of whether the read data is pass or fail, and performing a read-retry operation comprising applying the read current of the second level to the nonvolatile memory cell.

Method of operating nonvolatile memory device comprising resistance material

A nonvolatile memory device utilizes a variable resistive element. The nonvolatile memory device includes a plurality of banks and first to third write global bit lines arranged to cross the plurality of banks. Each of the plurality of banks includes a plurality of nonvolatile memory cells using resistive material. The first, the second and the third write global bit lines are disposed directly adjacent to one another in order. When a write current is supplied to the first write global bit line during a write period, a fixed voltage is applied to the second write global bit line while the third global bit line floats.

Nonvolatile memory device using variable resistive element

A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator configured to generate a first voltage, a voltage pad configured to receive an external voltage that has a level higher than the first voltage, a write driver configured to be supplied with the external voltage and configured to write data to the plurality of non-volatile memory cells selected from the memory cell array; a sense amplifier configured to be supplied with the external voltage and configured to read data from the plurality of non-volatile memory cells selected from the memory cell array, and a row decoder and a column decoder configured to select the plurality of non-volatile memory cells included in the memory cell array, the row decoder being supplied with the first voltage and the column decoder being supplied with the external voltage.

Non-volatile memory device using variable resistance element with an improved write performance

Growing community of inventors

Hwaseong-si, South Korea

Kwang-Jin Lee