Samsung Electronics Co., Ltd.

Seoul Semiconductor Co., Ltd.

Hyundai Motor Company

Kwang-il Park

Seung-Jun Bae

Young-Soo Sohn

Seong-Jin Jang

Chul-woo Park

Woo-Jin Lee

Jae-Youn Youn

Jeong-Don Lim

Si-Hong Kim

Sang-Uhn Cha

Tae-Young Oh

Ho-Young Song

Kyoung-Ho Kim

Hyun-jin Kim

Jong-Pil Son

Hoi-ju Chung

Hyun-Jin Kim

Sang-hyup Kwak

Jin-gook Kim

Do-Hyung Kim

Tae-young Kim

Chung-Hoon Lee

Young-Hun Seo

Jin-il Lee

Dong-min Kim

Hye-Ran Kim

Ho-young Song

Sei-jin Kim

Sung-Hoon Kim

Young-Hyun Jun

Hak-soo Yu

Dae-hyun Kim

Seung-ju Kim

Ho-Seok Seol

Tae-ho Lee

In Huh

Keon-Young Lee

Youn-sik Park

Su-Yeon Doo

Hyo-jin Choi

Chang-wook Jeong

Joon-wan Chai

Jeong-hoon Ko

Hyun-sun Park

Young-min Oh

Jun-haeng Lee

Dae-Hyun Kim

Hyun-Joong Kim

Dong-Min Kim

Uk-Song Kang

Joung-Yeal Kim

Dae-Jeong Kim

Young-chul Cho

Seung-Jun Shin

Su-a Kim

Sang-woong Shin

In-Chul Jeong

Ji-Hoon Lim

Lee-Sup Kim

Joo-Sun Choi

Eun-sung Seo

Young-soo Sohn

Mi-Jin Lee

Byung-Guk Kim

Yong-Gwon Jeong

Kyung-hyun Kim

Young-Hoon Sohn

Hyun-Dong Kim

Dae-Sun Kim

Hye-Jung Kwon

Gil-Shin Moon

Kwan-Young Han

Seung-Man Yang

Hong-San Kim

Tae-young Oh

Sung-Min Ryu

Yun-Seok Yang

A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Device for generating verification vector for circuit design verification, circuit design system, and reinforcement learning method of the device and the circuit design system

A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Memory device that performs internal copy operation

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

Memory devices and methods of operating the same are provided. The memory device including at least one internal circuit including a memory cell array and a peripheral circuit configured to drive the memory cell array, a monitor logic configured to monitor a current flowing into the at least one internal circuit and output a monitoring result, a detect logic configured to detect whether a leakage current flows in the at least one internal circuit based on the monitoring result, and output detected information regarding the leakage current, and diagnosis logic configured to diagnose an error in the at least one internal circuit based on the detected information.

Memory device, memory system, and operating method of memory device

A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

Semiconductor memory devices, memory systems including the same and method of correcting errors in the same

Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a 'fail' cell by using an error correction code (ECC) operation, and also repairs the 'fail' cell by using a redundancy repair operation when the &#x2018;fail&#x2019; cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the &#x2018;fail&#x2019; cell, and may also change the size of parity bits regarding the changed codeword.

Memory device for performing error correction code operation and redundancy repair operation

A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Semicondutor memory device and memory system including the same

A memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a plurality of dynamic memory cells. The memory controller controls the semiconductor memory device. The memory controller applies an auto-refresh command to the semiconductor memory device at each refresh interval of the semiconductor memory device such that the semiconductor memory performs a refresh operation in a normal mode, and does not apply the auto-refresh command to the semiconductor memory device during a self-refresh interval in which the semiconductor memory performs a self-refresh operation. After the semiconductor memory device exits from the self-refresh interval, the memory controller adjusts an application of the auto-refresh command in the normal mode by reflecting information of the self-refresh interval.

Memory systems that adjust an auto-refresh operation responsive to a self-refresh operation history

A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.

Method of refreshing memory device

A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Memory device and memory system having the same

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Yongin-si, South Korea

Kwang-il Park