Samsung Electronics Co., Ltd.

Kwang-il Kim

Jin Sung Kim

Byung-Sun Kim

Hee-Sung Kang

Young-Gun Ko

Young-wug Kim

Min-su Kim

Sung-bae Park

Kyoung-kuk Chae

Sung-yun Kang

A semiconductor device may include a logic circuit and one or more power gating transistor switches. The logic circuit may be connected between a power voltage and a ground voltage, and may perform one or more logic operations. The one or more power gating transistor switches may include a plurality of power gating transistors and poly resistors, and may switch application of the power voltage to the logic circuit according to an active mode, a sleep mode, or active and sleep modes of the logic circuit. The one or more power gating transistor switches may use the poly resistors to sequentially apply the power voltage to the logic circuit, to sequentially block the application of the power voltage to the logic circuit, or to sequentially apply the power voltage to the logic circuit and to sequentially block the application of the power voltage to the logic circuit.

Layout schemes and methods of power gating transistor switches, semiconductor devices including the power gating transistor switches, and power gating methods of the semiconductor devices

A processor chip having a cache hit logic for determining whether data required by a processor is stored in a cache memory includes a dummy cell string that operates the same as a sense amplifier for sensing a tag address stored in a tag memory cell array and a comparison logic for determining whether the sensed tag address coincides with an input tag address, a dummy sense amplifier, and a dummy comparison logic. The processor chip having the cache hit logic improves the reliability of a hit signal and operation speed is not limited.

Cache hit logic of cache memory and processor chip having the same

The present invention relates to a semiconductor test device which may use a leakage current and/or a compensation system of leakage current. The semiconductor test device, according to exemplary embodiments of the present invention, may include MOS transistors which may be fabricated in processes similar to those of the semiconductor device. The semiconductor test device may sense the leakage currents which may flow in the MOS transistors, may test whether the semiconductor device may be fabricated normally or abnormally, and may generate at least a normal or abnormal signal as a result. The leakage current compensation device may compensate for the leakage current which may flow in the semiconductor device in response to the normal or abnormal signal of the semiconductor test device. According to exemplary embodiments of the present invention, abnormally-fabricated MOS transistors may be tested and malfunctions of the semiconductor device may be reduced by the leakage current compensation device.

Semiconductor test device using leakage current and compensation system of leakage current

A cache hit logic for determining whether data required by a processor is stored in a cache memory includes a dummy cell string that operates the same as a sense amplifier for sensing a tag address stored in a tag memory cell array and a comparison logic for determining whether the sensed tag address coincides with an input tag address, a dummy sense amplifier, and a dummy comparison logic. The cache hit logic improves the reliability of a hit signal and operation speed is not limited.

Cache hit logic of cache memory

A semiconductor wafer transfer apparatus includes a wafer supporting block to support a semiconductor wafer, a casing which is formed along a moving path of the wafer supporting block and having a guiding slot through which a part of the wafer supporting block passes, a driving part which is accommodated in the casing and moves the wafer supporting block, a connection part which connects the driving part with the wafer supporting block, and a shield part which shields the driving part from the guide slot. Accordingly, dust and particles generated inside the casing is effectively prevented from leaking out through the guide slot.

Semiconductor wafer transfer apparatus

A skew-free dual rail bus driver is provided. The dual rail bus driver includes a first driver outputting first dual signals of the same level, and outputting second dual signals of different levels when a level of a clock changes; a decoder receiving the second dual signals and outputting a single signal; a dual signal controller being triggered due to a change in the level of the second dual signals and outputting third dual signals of different levels in response to the single signal at the same time; and a second driver inverting the levels of the third dual signals output from the dual signal controller and outputting fourth dual signals in accordance with a change in the level of the clock. Accordingly, it is possible to obtain dual rail bus driving signals in which skew does not occur. Also, changes in the phases of dual signals are detected and used as a trigger signal input to an edge trigger flip-flop which is a dual signal controller. Also, signals output from the edge trigger flip-flop are used as dual rail bus driving signal, instead of using a clock delayer.

Skew-free dual rail bus driver

A cache memory device and method are provided with a word line driver circuit that can increase the operational speed of the cache memory device and yield a reduction in the chip area of a semiconductor integrated circuit, where a cache memory device includes a first memory cell block, a second memory cell block, a plurality of first content addressable memory (&ldquo;CAM&rdquo;) cells, a plurality of second CAM cells, a first word line driver circuit, and a second word line driver circuit; and a corresponding method provides that the plurality of first content addressable memory (&ldquo;CAM&rdquo;) cells stores a tag address of the first memory cell block commonly connected to a first dynamic node, and the plurality of second CAM cells stores a tag address of the second memory cell block commonly connected to a second dynamic node; the first and second dynamic nodes are initially precharged to a predetermined level; the precharged predetermined level of one of the first and second dynamic nodes is maintained and the other one is discharged when an address is input from a CPU; and in particular, the first word line driver circuit activates the word line of the first memory cell block when the predetermined level of the first dynamic node is maintained and the second dynamic node is discharged, and the second word line driver circuit activates the word line of the second memory cell block when the predetermined level of the second dynamic node is maintained and the first dynamic node is discharged.

Cache memory device including word line driver circuit and method

A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

Growing community of inventors

Suwon-si, South Korea

Kwang-il Kim