Hynix Semiconductor Inc.

Skhynix Inc.

Samsung Display Co., Ltd.

Kwang-Hyun Kim

Dae Won Kim

Ji-Hoon Kim

Seung Beom Park

Sang-Gu Lee

Hee Wook Do

Duck Jong Suh

Kang-Youl Lee

Boo-Kan Ki

Na Young Shin

Gwan Young Na

Teck Soo Kim

Sang-Hui Kim

A semiconductor device includes a memory region suitable for providing a plurality of read data in parallel at every read operation cycle, an output path suitable for outputting the plurality of read data at a set time in response to an internal clock and one or more internal control signals at the every read operation cycle, and an output path control unit suitable for generating the internal control signal in response to a read command and generating the internal clock in response to a system clock, wherein a shifting time of a first edge of the internal clock is adjusted by a set level at the every read operation cycle during a test mode.

Semiconductor device, semiconductor system including the same and test method thereof

A pulse generation circuit includes a control unit configured to activate one or more of control clocks among a plurality of control clocks, and to activate one or more of select signals among a plurality of select signals, in response to one or more of sequence signals; a plurality of shifting units each configured to generate one or more of output signals, and to sequentially activate the one or more of output signals by shifting an input pulse when a corresponding control clock among the plurality of control clocks is activated; and a signal transfer unit configured to transfer one or more of output signals of a shifting unit corresponding to an activated select signal among the plurality of shifting units, as one or more of pulses.

Pulse generation circuit, burst order control circuit, and data output circuit

Provided is a semiconductor memory device in which a plurality of first and second data lines coupled to a memory cell array are alternately arranged. The semiconductor memory device includes a first write driving circuit configured to load a plurality of first write data transmitted through a plurality of third data lines into the plurality of first data lines in response to a first write enable signal; a second write driving circuit configured to load a plurality of second write data transmitted through a plurality of fourth data lines into the plurality of second data lines in response to a second write enable signal; and a column control circuit configured to activate at least one of the first and second write enable signals during a given period, in response to a plurality of data width option modes, during a parallel test mode.

Semiconductor memory device and method of testing the same

A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.

Data output circuit of semiconductor memory device

A data input buffer control signal generating device is capable of preventing unnecessary operation and current consumption of blocks and thus stabilizing an internal operation of DRAM by generating a control signal which controls an enabling timing of a data input buffer not to be conflicted with an output data. The data input buffer control signal generating device includes a write-related control unit configured to generate a data input buffer reference signal generated on the basis of a write latency by a write command, a read-related control unit configured to replicate a delay through a data output path, delay an end command for a data output termination and generate a delayed end command, wherein the end command is generated by a read command, and an output unit configured to output a data input buffer control signal by combining the data input buffer reference signal and the output of the delayed end command.

Circuit and method for generating data input buffer control signal

A semiconductor memory device includes data transmission devices for transmit data in synchronization with each other. The semiconductor memory device includes a plurality of data transferring unit, a first control unit, a multiplexing unit, and a second control unit. The plurality of data transferring unit transfers data to a plurality of global lines. The first control unit controls the plurality of data transferring unit in response to a column select signal to select a column of a memory cell. The multiplexing unit multiplexes the data transferred to the plurality of global lines. The second control unit controls the multiplexing unit, wherein the second control unit synchronizes the column select signal with a column address signal having a column address information of the memory cell.

Semiconductor memory device

A circuit for controlling the loading of write data in a semiconductor memory device includes a global bus; a data block configured to selectively load data of a predetermined first burst length or data of a second burst length, which is a half of the first burst length, for writing on the global bus in response to a control signal; and a memory bank configured to write the data of the first burst length or the data of the second burst length.

Circuit and method for controlling loading of write data in semiconductor memory device

A burst order control circuit includes a burst signal generating unit configured to receive a seed column address and to generate a first rising burst signal, a second rising burst signal, a first falling burst signal and a second falling burst signal in response to the seed column address, and a repeater unit configured to transfer the first rising burst signal, the second rising burst signal, the first falling burst signal and the second failing burst signal to a pipe latch.

Burst order control circuit and method thereof

A semiconductor memory device reduces power consumption during a refresh operation. The semiconductor memory device comprises a voltage generator, a sensing controller, an output driver and a data transmitter. The voltage generator is configured to generate an internal power voltage, which is lower during a power saving mode than during a normal mode, for a peripheral area. The sensing controller is configured to generate a control signal corresponding to a level of the internal power voltage. The output driver is configured to drive a transmitting data by using an output voltage. The data transmitter is configured to convert an inputting data into the transmitting data by using the internal power voltage or convert the inputting data into the transmitting data by using the output voltage in response to the control signal.

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Gyeonggi-do, South Korea

Kwang-Hyun Kim