Samsung Electronics Co., Ltd.

Texas Instruments Corporation

Fairchild Korea Semiconductor Ltd.

Trinno Technology Co., Ltd.

Kwang-Hoon Oh

Chong-man Yun

Charvaka Duvvury

Min-Koo Han

Kyu-hyun Lee

Soo-Seong Kim

Deok-Joong Kim

Byoung-Ho Choo

Young-chull Kim

A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.

MOS gate power semiconductor device with anode of protection diode connected to collector electrode

Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type. A collector region of the second conductivity type is formed on the ground surface of the semiconductor substrate of the FS region, thereby forming an FS-IGBT.

Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same

An MOS transistor in the surface of a semiconductor substrate ( ) of a first conductivity type, which has a grid of isolations ( ) in the surface, each grid unit surrounding a rectangular semiconductor island ( ). Each island contains three parallel regions of the opposite conductivity type: the center region ( ) is operable as the transistor drain and the two other regions ( and ), abutting the isolations, are operable as transistor sources. Transistor gates ( and ) are between the parallel regions, completing the formation of two transistors having one common drain. Electrical contacts ( ) are placed on both source regions and the drain region. The source contacts are placed so that the spacing ( ) between each contact and its respective isolation is at least twice as large as the spacing ( ) between each contact and the gate. A plurality of these islands are interconnected to form a multi-finger MOS transistor having increased ESD failure threshold current by spreading the power dissipation and thus reducing the current localization without impacting the drain-to-substrate capacitance.

Geometry-controllable design blocks of MOS transistors for improved ESD protection

An MOS transistor in the surface of a semiconductor substrate ( ) of a first conductivity type, which has a grid of isolations ( ) in the surface, each grid unit surrounding a rectangular substrate island ( ). Each island contains two parallel regions of the opposite conductivity type: one region ( ) is operable as the transistor drain and the other region ( ) is operable as the transistor drain, each region abutting the isolation. A transistor gate ( ) is between the parallel regions, completing the formation of a transistor. Electrical contacts ( ) are placed on the source region ( ) so that the spacing ( ) between each contact and the adjacent isolation is at least twice as large as the spacing ( ) between each contact and the gate. A plurality of these islands are interconnected to form a multi-finger MOS transistor. The source contact spacings are selected to increase the failure threshold current of the multi-finger MOS transistor by spreading the power dissipation and thus reducing the current localization, whereby the protection of the transistor against ESD pulses is improved.

Spreading the power dissipation in MOS transistors for improved ESD protection

An insulated gate bipolar transistor according to the present invention has a first and a second emitter regions. A diffusion region of the first conductive type is formed in the first emitter region of the second conductive type. The second emitter region has a region having a high concentration compared with the remaining portion of the second emitter region. The high concentration region is adjacent to the diffusion region and positioned towards the center of a first conductive type well. In addition, the junction depth of the high concentration region is similar to the diffusion region.

Insulated gate bipolar transistor

An emitter switched thyristor has an enlarged safe operating range. A semiconductor substrate of a first conductivity type (a p-type) is provided and a semiconductor region of a second conductivity type (an n-type) is formed on the substrate. A well region of the first conductivity type is formed within the semiconductor region, and a plurality of well subregions of the second conductivity type are formed within the well region. The well subregions are all separated from each other by a separating portion of the well region. A plurality of electrode contacts are provided, including a gate electrode in contact with the well region and at least first and second cathode electrodes. The second cathode electrode is in contact with the separating portion of the well region.

Emitter switched thyristor

The present invention relates to a method of manufacturing an insulated-gate transistor including a very thin P.sup.- layer as a channel under a gate terminal. The device and method differs from conventional devices and techniques in that the P.sup.- regions are formed by double diffusion. Secondly, the present invention includes channel regions by forming the N.sup.+ regions in the middle of the shallow P.sup.- layer causing the resistance of the JFET regions to be reduced. High-speed operation of the device can be obtained by reducing the input and reverse capacitances which thereby reduces the time delay when power is supplied. The forward voltage drop is reduced by reducing the resistance of the first conductive semiconductor region which is determined by the distance between the second conductive type semiconductor region in its forward turn-on state.

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Seoul, South Korea

Kwang-Hoon Oh