Micron Technology Incorporated

Kwang-Ho Cho

Hiroshi Akamatsu

Miki Matsumoto

John David Porter

Kevin J Ryan

Bryan David Kerstetter

Systems and methods for providing memory access commands to memory circuitry using a gap controlled multi-clock cycle memory command protocol is described. More than one memory commands are combined into one multi-clock cycle memory command using gap controlled multi-clock cycle memory command protocol. The number of clock cycles included in the gap between two clock cycles in the multi-clock cycle memory command is controlled and adjustable.

Hybrid gap controlled multi-clock cycle memory command protocol

Methods, systems, and devices for triple activate command row address latching are described. For instance, a memory device may receive a first activate command that indicates a first set of bits of a row address, a second activate command that indicates a second set of bits of the row address, and a third activate command that indicates a third set of bits of the row address. The memory device may activate a page of memory based on receiving the first activate command, the second activate command, and the third activate command, where the page of memory is addressed according to the first set of bits, the second set of bits, and the third set of bits.

Triple activate command row address latching

Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.

Row address latching for multiple activate command protocol

A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

Activate information on preceding command

Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

Command triggered power gating for a memory device

Systems and methods for providing memory access commands to memory circuitry using a multi-clock cycle memory command protocol is described. A command decoder (or controller) of the memory circuitry may efficiently receive a memory access request (or a memory command) provided using multiple clock cycles. For example, the command decoder may receive a header and a first portion of address bits of target memory cells of the memory command in a first clock cycle and a second portion of the address bits of the target memory cells in a subsequent clock cycle. Accordingly, the memory circuitry may receive a memory command provided over multiple clock cycles with one header. Such memory commands may efficiently include a high number of address bits received using input circuitry of the memory circuitry.

Multi-clock cycle memory command protocol

Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

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Boise, ID, United States of America

Kwang-Ho Cho