Hynix Semiconductor Inc.

Skhynix Inc.

Kwang Ho Baek

Sam Kyu Won

Jae Won Cha

Ji Hwan Kim

Young Don Jung

Jung Mi Ko

Jung Hwan Lee

Seong Jin Park

In Ho Kang

Jin Su Park

Jong Hoon Lee

Chang Won Yang

Sung Hoon Ahn

Chang Hyuk Lee

Go Hyun Lee

Jin Haeng Lee

Chang Man Son

Tai Sik Shin

Chang Han Son

Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.

Semiconductor memory device and method for operating thereof

The present technology relates to a memory device and method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit performs a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells. The control logic controls the peripheral circuit to increase a potential of selected bit lines.

Memory device and method of operating the memory device

A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.

Memory device and operating method thereof for applying a channel precharge voltage to bit lines after a sensing operation

Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.

Page buffer, a memory device having page buffer, and a method of operating the memory device

A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.

Semiconductor memory device and operating method thereof

The present disclosure relates to a memory device and a memory system including the same. The memory device includes a memory cell storing data, a voltage generation circuit selectively outputting a program voltage and verify voltages in response to an operation control signal, a page buffer including first latches and second latches, and storing first data sensed by a first sensing current in the first latches and second data sensed by a sensing current greater than the first sensing current in the second latches during a verify operation using the verify voltages, and a pass/fail check circuit determining a pass or fail of the verify operation of the memory cell according to the first data and allowable bits.

Memory device, memory system including the memory device

A method of operating a memory device having improved threshold voltage distributions of select transistors, the memory device including a plurality of cell strings each including a plurality of source select transistors, a plurality of memory cells, and a plurality of drain select transistors stacked in a vertical direction to a substrate include performing a first program operation to program at least one source select transistor coupled to a first source select line adjacent to a common source line, among the plurality of source select transistors, using a fixed program voltage, and performing a second program operation to program at least one source select transistor coupled to a second source select line adjacent to the first source select line, among the plurality of source select transistors, using an incremental step pulse program (ISPP) method after the first program operation is completed.

Memory device having plurality of memory cell strings, plurality of source select transistors and plurality of drain select transistors and method of operating a memory device having improved threshold voltage distributions of select transistors

A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to couple local lines of the memory block to global lines. The first to third conductive patterns are arranged in different layers over the memory block.

Semiconductor apparatus

A method of erasing charge trap devices includes applying a first erase voltage to the charge trap devices; applying an erase verify voltage to the charge trap devices; performing a current first fail bit check operation including comparing a first number of charge trap devices, which are determined to be an erase fail based on the erase verify voltage, to a first reference value and determining a pass or fail based on the comparison result; when the current first fail bit check operation is determined to be a fail, determining whether a previous first fail bit check operation performed during a previous erase loop was passed or not; and when the previous first fail bit check operation performed during the previous erase loop was passed, setting a third erase voltage to a same level as a second erase voltage used during the previous erase loop.

Method for erasing charge trap devices

A semiconductor device includes cell strings that each include a plurality of memory cells, a page buffer having latches coupled to bit lines and precharge the bit lines in response to page buffer control signals, a page buffer control circuit configured to generate the page buffer control signals using a high voltage source, and a controller configured to generate control signals for controlling the page buffer control circuit.

Semiconductor device and method of operating the same

A semiconductor device including a memory block, which includes memory cells coupled to bit lines. The semiconductor device further includes a first sensing circuit coupled to an even bit line and configured to sense current flow through the even bit line in response to an even bit line control signal and an even discharge signal. The semiconductor device further includes a second sensing circuit coupled to an odd bit line and configured to sense current flow through the odd bit lines in response to an odd bit line control signal and an odd discharge signal. The first sensing circuit and second sensing circuit are configured to supply a ground voltage to the odd bit line when sensing the current flow through the even bit line, and to supply the ground voltage to the even bit line when sensing the current flow through the odd bit line.

An erase operation of a memory apparatus is controlled by, inter alia, selecting one or more memory cell blocks to be erased among a plurality of memory cell blocks, performing an erase operation on the selected one or more memory cell blocks in response to an erase command, performing a first soft program operation on the selected one or more memory cell blocks if the erase operation is determined as passed, and performing a second soft program operation on the selected one or more memory cell blocks if the first soft program operation is determined as passed.

Memory apparatus and method for controlling erase operation of the same

A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller.

Method of operating a flash memory device

A method of operating a nonvolatile memory device includes reading data stored in a main cell and a flag cell using a first read voltage, the nonvolatile memory device comprising the main cell for storing data including a least significant bit (LSB) and a most significant bit (MSB), and the flag cell for determining a program state of the main cell, determining a program state of the main cell based on the data read from the flag cell, reading data stored in the main cell and the flag cell using a second read voltage if a MSB page program has been performed on the main cell, and reading data stored in the main cell using a third or a fourth read voltage based on the data read from the flag cell using the second read voltage, if a threshold voltage of the main cell shifts.

Growing community of inventors

Icheon-si, South Korea

Kwang Ho Baek