Samsung Electronics Co., Ltd.

Kwang Hee Choi

Jaegeun Park

Oh Sung Kwon

Tae Min Jeong

Dae Sik Park

Young Ho Kwak

Joonsung Bae

A PCIe capable semiconductor device includes; ports respectively configured to transmit and receive data in a PCIe environment, and a PCIe controller configured to set a link between the PCIe capable semiconductor device and another PCIe capable semiconductor device. The link includes at least one lane implemented over at least one of the ports. The PCIe controller includes a link training and status state machine (LTSSM) configured to perform a first lane number negotiation according to a first ordering of the ports and a second lane number negotiation according to a second ordering of the ports different from the first ordering of the ports, and determine an optimized link width for the link according to the results of the first lane number negotiation and the second lane number negotiation.

Semiconductor device, method of operating semiconductor device and system incorporating same

A PCIe device for supporting SRIS includes a transceiver, a clock signal generator configured to generate a second reference clock signal, a connector in a structure to be connected to a PCIe host, and a selection circuit configured to determine whether a first reference clock signal is supplied through the connector and transmit one of the first reference clock signal and the second reference clock signal to the transceiver according to a result of the determination.

PCIe device for supporting with a separate reference clock with independent spread spectrum clocking (SSC)(SRIS)

A semiconductor device can reduce power consumption in a low power mode and includes a first input/output circuit configured to detect a first entry signal transiting at a first time and output a detection signal indicating an entry into a power saving mode according to a result of the detection. A second input/output circuit is configured to receive a second entry signal transiting at a second time earlier than the first time, and a control circuit is configured to block power supplied to the second input/output circuit in response to the detection signal indicating the entry.

Semiconductor device for reducing power consumption in low power mode and system including same

Provided is an interface circuit for transmitting and receiving data according to a communication protocol. The interface circuit includes: an encoder configured to encode input data to generate transmission data; a transmitter configured to output the transmission data; a data sequence detector configured to detect whether the number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number; and a recovery section configured to control a recovery operation with respect to the transmission data, based on a detection result of the data sequence detector. With the interface circuit, data loss is prevented and data reliability is guaranteed.

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Seoul, South Korea

Kwang Hee Choi