Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Other

Kwang-Eui Pyun

Deok-Ho Cho

Soo-Min Lee

Byung-Ryul Ryum

Tae-Hyeon Han

Chul-Sun Park

Jin-Hee Lee

Byung-Sun Park

Hyung-Sup Yoon

Jeon-Wook Yang

Kyung-Soo Kim

Jae-Jin Lee

Kyung-Ho Lee

Chul-Soon Park

Eung-Gie Oh

Sung-Jae Maeng

Eung-Gee Oh

Youn-Kyu Bae

The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Method for fabricating of super self-aligned bipolar transistor

A method for fabricating a T-shaped gate electrode of a high speed semiconductor device such as HEMTs which is applied to high speed logic circuit including low-noise receivers and power amplifiers having a frequency of X-band or more respectively, and MMICs having a frequency of millimeter wave band. Such devices require a short gate length and a large sectional area of the gate pattern. The conventional photolithography techniques are in need of the resolution for fabricating a fine line width. Therefore, electron-beam lithography is most widely used. But, it is difficult to enhance throughput in manufacturing semiconductor devices because a lot of exposure time is required in the methods using electron beams. In the present invention, a silicon oxide film or a silicon nitride film is deposited on a mono-layered resist pattern. A dummy pattern corresponding to a leg of the gate is formed using the silicon oxide film or the silicon nitride film. A leg of the gate electrode is formed at the portion of the dummy pattern. According to the present invention, a step for improving the resolution is not required, and a gate electrode having a very fine line width of a few hundreds .ANG. can be obtained by regulating the thickness of the silicon nitride film.

Fabrication method of T-shaped gate electrode in semiconductor device

Super self-aligned bipolar transistor

This invention provides infrared sensing photodetector and a method therefor which provides a structure for effectively absorbing a light incident in a normal direction on a substrate, and a method compatible with existing processes for making integrated circuitry. An infrared sensing photodetector includes a compound semiconductor substrate of a first conductivity type, superlattice areas having implanted impurity ions of a second conductivity type opposite to the compound semiconductor substrate, each being spaced a predetermined distance each other in a selected region of the semiconductor substrate, a first collector area and a first emitter area which are formed in both end portions positioned perpendicular relative to the doped superlattice areas, a first collector electrode and a first emitter electrode formed on the first collector area and the first emitter area, respectively, a second collector area and a second emitter area which are spaced a predetermined distance in a horizontal direction on the doped superlattice area, and a second collector electrode and a second emitter electrode formed on the second collector area and the second emitter area, respectively.

Infrared photodetector with doping superlattice structure

The invention relates to a method of fabricating a compound semiconductor device by forming a first and a second compound semiconductor devices having a plurality of different epitaxial layers on a common semiconductor substrate. The method comprises the steps of sequentially forming a plurality of first epitaxial layers for manufacturing the first compound semiconductor device on the semiconductor substrate; forming a first insulating film pattern for defining an active region of the first compound semiconductor device; etching the plurality of first epitaxial layers using the first insulating film pattern as a mask; forming a second insulating film on the resultant structure; forming a sidewall insulating spacer on the sidewall of the active region of the first compound semiconductor device by dry etching the second insulating film; sequentially forming a plurality of second epitaxial layers for manufacturing the second compound semiconductor device on the portion from which the plurality of first epitaxial layers is etched back; forming each electrode of the first and second compound semiconductor devices; and forming an interconnection electrode interconnecting each electrode of the first and second compound semiconductor devices.

Method of fabricating a compound semiconductor device

A fabrication method of a semiconductor device is disclosed. A T-shaped gate used for decreasing the gate resistance is adopted in fabricating an ultrahigh frequency and low-noise device. According to the present invention, a gate pattern is formed by a dual exposure technique, a thin metal film is formed, a pattern for plating is formed, and a gate is formed by electroplating, whereby decreasing a gate length and gate resistance. Therefore, the cost of production is decreased, the yield is improved, and the noise figure is minimized.

Fabrication method of gate electrode in semiconductor device

A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.

Method for fabricating T-shaped electrode and metal layer having low

An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the base electrode polysilicon layer on the shallow trench, and forming a self-aligned base.

Method for fabricating heterojunction bipolar transistor

A method for isolating a semiconductor device is disclosed including the steps of sequentially growing a plurality of material layers on a semiconductor substrate, etching the material layers down to a predetermined depth of the substrate to thereby define an active region, forming a semi-insulating film on the exposed semiconductor substrate in order to planarize the step-difference of the active region and the isolation region, and then, forming an ohmic metal layer on a space where the semi-insulating film is regrown.

Method for isolating semiconductor device

The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth and a polycide base electrode without using a trench for isolating between elements, thereby enhancing the performance thereof, which comprises the steps of: forming sequently a first oxidation film, an electrically conducting thin film and a second oxidation film on top of a substrate; patterning the second oxidation film and the conducting thin film to form a preliminary spacer; removing an exposed portion of the first oxidation film, and selectively growing a collector layer; oxidizing the collector layer to form a thermal oxidation film, and removing the preliminary spacer; depositing a polysilicon and forming a silicon oxidation film and a polysilicon spacer on the second oxidation film and the removed portion of the preliminary spacer, respectively; exposing the base thin film, the spacer and the collector layer to form a SiGe/Si layer; forming a base electrode on the SiGe/Si layer; exposing a portion of the first oxidation film and forming a third oxidation film; exposing a surface of the SiGe/Si layer and forming a oxidation spacer on sides of an etched portion, then self-aligning the emitter and the emitter electrode; and performing a metal wiring process.

Method for manufacturing a super self-aligned bipolar transistor

A silicon/silicon-germanium bipolar transistor fabrication method employs a metallic silicide film as an extrinsic base electrode to reduce resistance of the extrinsic base electrode, and to increase a maximum oscillation frequency and cut-off frequency due to its self-aligned structure. The fabrication method enables agglomeration to occur on the side wall of the polycrystalline silicon film connected to the metallic silicide film instead of on the interface between the metallic silicide film and the lower silicon/silicon-germanium film, and leads the extrinsic base electrode to be sandwitched by the insulator films, thereby realizing a constant resistance and also resulting in the application of integrated circuits to a mass production mechanism.

Silicon-silicon-germanium heterojunction bipolar transistor fabrication

Disclosed is a method of fabricating a metal semiconductor field effect transistor, comprising the steps for, forming the channel using an ion-implantation, sequentially forming a first insulator layer at a first predetermined temperature and a second insulation layer at second predetermined temperature over the surface of the substrate, etching the first and second insulation layers using a gate pattern of a photo-resist pattern to expose the channel region as a mask, forming a refractory metal over the surface of the first and second insulation layer add the exposed channel region, etching the refractory metal, thereby dividing it into two parts of which one is formed on the channel region and the other is formed on the second insulation layer, selectively etching the first and second insulation layers to lift-off the refractory metal over the first and second insulation layers, thereby forming a gate of a T-shape on the channel region, ion implanting Si into a substrate using the gate and a channel pattern of a photo-resist film to form a self-aligned high concentration ion implantation region, forming a third insulation layer for preventing As of evaporation, carrying out a rapid thermal annealing for activation, removing the third insulation layer; and forming an ohmic electrode using a lift-off process.

Growing community of inventors

Daejeon, South Korea

Kwang-Eui Pyun