Samsung Electronics Co., Ltd.

Kwang Chul Park

Yong-Hoon Son

Kohji Kanamori

Kyung-Hyun Kim

Kyung Hyun Kim

Phil Ouk Nam

Yong Hoon Son

Jong-Heun Lim

Phil-Ouk Nam

Yeon-Sil Sohn

Ji Woon Im

Hyun Seok Lim

Jin-I Lee

Won-Bong Jung

Jin Il Lee

Il Woo Kim

Dai Hong Kim

Won Bong Jung

Byeong Ju Kim

Byeong-Ju Kim

Jong Heun Lim

Yeon Sil Sohn

A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.

Deposition apparatus including UV annealing unit and method for fabricating non-volatile memory device by using the deposition apparatus

A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

Vertical memory devices

A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.

Memory device and method of manufacturing the same

Growing community of inventors

Suwon-si, South Korea

Kwang Chul Park