Globalfoundries Inc.

International Business Machines Corporation

Kwan-Yong Lim

Min Gyu Sung

Steven J Bentley

Ruilong Xie

Chanro Park

John H Zhang

Ryan Ryoung-Han Kim

Hui Zang

Hiroaki Niimi

Christopher Michael Prindle

Hoon Sik Kim

Chun Yu Wong

Seong Yeol Mun

Brent A Anderson

Junli Wang

Carl John Radens

Daniel Chanemougame

Jagar Singh

Bipul C Paul

Manfred Eller

Sukwon Hong

Brian Alexander Cohen

Haiting Wang

Andy C Wei

Yi Qi

Jody Alan Fronheiser

William James Taylor, Jr

Deepak K Nayak

Jianwei Peng

Hsien-Ching Lo

Youngtag Woo

Hui Zhan

Motoi Ichihashi

Mira Park

Kijik Lee

Amitabh Jain

One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.

Vertically oriented metal silicide containing e-fuse device

A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PUand PU) transistors, and first and second pull-down (PDand PD) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PUand PU. A second bottom electrode connects bottom SD regions of PDand PD. A first shared contact connects the top SD region of PUto the gate structure of PU. A second shared contact connects the top SD region of PDto the gate structure of PD. A first top electrode is connected to the top SD regions of PG, PUand the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG, PUand the first shared contact to define a second storage node of the memory cell.

Vertical transistor static random access memory cell

A vertical SRAM cell includes a first (1) inverter having a 1common gate structure operatively connecting channels of a 1pull-up (PU) and a 1pull-down (PD) transistor. A 1metal contact electrically connects bottom source/drain (S/D) regions of the 1PU and 1PD transistors. A second (2) inverter has a 2common gate structure operatively connecting channels of a 2PU and a 2PD transistor. A 2metal contact electrically connects bottom S/D regions of the 2PU and 2PD transistors. A 1cross-coupled contact electrically connects the 2common gate structure to the 1metal contact. The 2common gate structure entirely surrounds a perimeter of the 1cross-coupled contact. A 2cross-coupled contact electrically connects the 1common gate structure to the 2metal contact. The 1common gate structure entirely surrounds a perimeter of the 2cross-coupled contact.

Method of manufacturing a vertical SRAM with cross-coupled contacts penetrating through common gate structures

One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

Vertically oriented metal silicide containing e-fuse device and methods of making same

A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.

Self-aligned single diffusion break isolation with reduction of strain loss

A method of forming a 14 nm triple gate by adding a MG in the dual gate process and the resulting device are provided. Embodiments include forming an EG region, a MG region and a SG region in a first, second and third portions of a Si substrate, respectively; forming an IL over the EG, MG and SG regions; oxidizing the IL; forming a HK dielectric layer over the IL; performing PDA on the HK dielectric layer; forming a PSA TiN layer over the HK dielectric layer; forming an a-Si cap layer over the PSA TiN layer; forming a photoresist over the a-Si cap layer in the EG and SG regions; removing the a-Si cap layer in the MG region, exposing the PSA TiN layer; stripping the photoresist; and annealing the a-Si cap and PSA TiN layers.

Triple gate technology for 14 nanometer and onwards

One illustrative method disclosed includes, among other things, forming a gate structure around a fin and above a layer of insulating material, forming a gate spacer adjacent the gate structure and a fin spacer positioned adjacent the fin above the insulating material, the fin spacer leaving an upper surface of the fin exposed, and performing at least one etching process to remove at least a portion of the fin positioned between the fin spacer, the fin having a recessed upper surface that at least partially defines a fin recess positioned between the fin spacer. In this example, the method further includes forming an epi semiconductor material on the fin recess and removing the fin spacer from adjacent the epi semiconductor material while leaving a portion of the gate spacer in position adjacent the gate structure.

Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device

Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.

Vertical channel field-effect transistor (FET) process compatible long channel transistors

At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

Methods, apparatus and system for STI recess control for highly scaled finFET devices

Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region. A first semiconductor fin is formed that projects from the first device region and a second semiconductor fin is formed that projects from the second device region. A vertical field-effect transistor is formed using the first semiconductor fin, and a saddle fin-type field-effect transistor is formed using the second semiconductor fin. A top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed relative to the top surface of the trench isolation in the first device region adjacent to the first semiconductor fin.

Integration of vertical field-effect transistors and saddle fin-type field effect transistors

Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

Formation of bottom junction in vertical FET devices

One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material.

Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a FinFET device

Vertical SRAM structure with cross-coupling contacts penetrating through common gates to bottom S/D metal contacts

At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression

At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.

Growing community of inventors

Niskayuna, NY, United States of America

Kwan-Yong Lim