Hynix Semiconductor Inc.

Skhynix Inc.

Kwan-Woo Do

Kee-Jeung Lee

Young-Dae Kim

Kyung-Woong Park

Deok-Sin Kil

Jin-Hyock Kim

Jeong-Yeop Lee

Han-Sang Song

Jae-Sung Roh

Ki-Seon Park

Yun-Hyuck Ji

Beom-Yong Kim

Seung-Mi Lee

Woo-Young Park

Seung-Jin Yeom

Ga-Young Ha

Ji-Hoon Ahn

Gil-Jae Park

Jae-Hyoung Koo

Mi-Hyoung Lee

Ja-Yong Kim

This patent document provides an electronic device including a semiconductor memory that can simplify a fabrication process and improve characteristics of a variable resistance element, and a method for fabricating the same. In one aspect, an electronic device including a semiconductor memory is provided, wherein the semiconductor memory includes: a substrate; a variable resistance element formed over the substrate and exhibiting different resistance states to store data; an interlayer insulating layer formed over the substrate to surround at least a portion of the variable resistance element; an upper electrode contact formed over the variable resistance element to penetrate a portion of the interlayer insulating layer and be in contact with the variable resistance element; and a metal wiring formed over the interlayer insulating layer, and configured to include a stacked structure of a tungsten layer and a barrier layer, wherein the barrier layer is in contact with the upper electrode contact and includes tungsten, boron and iridium.

Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory that includes: a variable resistance element formed over a substrate; and a carbon-containing aluminum nitride layer formed on sidewalls and in an upper portion of the variable resistance element.

An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer which is formed over a substrate; a contact plug which is coupled with the substrate by passing through the inter-layer dielectric layer and has a protruding portion over the inter-layer dielectric layer; a first variable resistance pattern which is formed over the contact plug; and a protective layer which covers the first variable resistance pattern and a portion of sidewalls of the contact plug in such a manner that the sidewalls of the contact plug are exposed.

A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.

Semiconductor device having buried bit line and method for fabricating the same

A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer.

Method for fabricating capacitor with high aspect ratio

A capacitor includes a pillar-type storage node, a supporter disposed entirely within an inner empty crevice of the storage node, a conductive capping layer over the supporter and contacting the storage node so as to seal an entrance to the inner empty crevice, a dielectric layer over the storage node, and a plate node over the dielectric layer.

Capacitor with pillar type storage node and method for fabricating the same

An electrode of a semiconductor device includes a TiCN layer and a TiN layer. A method for fabricating an electrode of a semiconductor device includes preparing a substrate, forming a TiCN layer, and forming a TiN layer.

Electrode of semiconductor device and method for fabricating capacitor

In a semiconductor device including a carbon-containing electrode and a method for fabricating the same, an electrode has a high work function due to a carbon-containing TiN layer contained therein. It is possible to provide a dielectric layer having a high permittivity and thus to reduce the leakage current by forming an electrode having a high work function. Also, sufficient capacitance of a capacitor can be secured by employing an electrode having a high work function and a dielectric layer having a high permittivity.

Semiconductor device including carbon-containing electrode and method for fabricating the same

A capacitor includes a lower electrode, a dielectric layer, an upper electrode, and a ruthenium oxide layer. At least one of the lower electrode and the upper electrode is formed of a ruthenium layer, and the ruthenium oxide layer is disposed next to the ruthenium layer.

Semiconductor device and method for fabricating the same

A noble metal layer is formed using ozone (O) as a reaction gas.

Method of forming noble metal layer using ozone reaction gas

A semiconductor device and a method of fabricating the same include an electrode having a nickel layer with impurities. The electrode having a nickel layer with impurities can be a gate electrode or a capacitor electrode. The electrode having a nickel layer with impurities may include a combination of a pure nickel layer and a nickel layer with impurities.

Method of fabricating capacitor

A semiconductor device, and a method of fabricating the semiconductor device, which is able to prevent a leaning phenomenon from occurring between the adjacent storage nodes. The method includes forming a plurality of multi-layered pillar type storage nodes each of which is buried in a plurality of mold layers, wherein the uppermost layers of the multi-layered pillar type storage nodes are fixed by a support layer, etching a portion of the support layer to form an opening, and supplying an etch solution through the opening to remove the multiple mold layers. A process of depositing and etching the mold layer by performing the process 2 or more times to form the multi-layered pillar type storage node. Thus, the desired capacitance is sufficiently secured and the leaning phenomenon is avoided between adjacent storage nodes.

Semiconductor device and method of fabricating the same

A capacitor includes a bottom electrode, a dielectric layer and a top electrode over a substrate. A RuTiOfilm is included in at least one of the bottom and top electrodes, where x, y and z are positive real numbers. A method of fabricating the capacitor through a sequential formation of a bottom electrode, a dielectric layer and a top electrode over a substrate includes forming a RuTiOfilm during a formation of at least one of the bottom electrode and top electrode, where x, y and z are positive real numbers.

Method of fabricating capacitor in semiconductor device

A method for fabricating a capacitor includes forming a sacrificial layer having a plurality of trenches on an upper portion of a substrate, forming storage nodes in the trenches, exposing upper portions of the storage nodes by removing a portion of the sacrificial layer, forming supporters to support the exposed upper portions of the storage nodes, removing the sacrificial layer under the supporters, and removing the supporters.

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Icheon-si, South Korea

Kwan-Woo Do