Dongbu Electronics, Co. Ltd.

Dongbu Anam Semiconductor, Inc.

Anam Semiconductor Inc.

Kwan-Ju Koh

The present disclosure improves characteristics and reliability of a device by preventing seams within a copper layer, wherein seams are created when forming a copper line by a damascene process. Such seams created within a first and a second copper layer are prevented by a process in which the first copper layer and the second copper layer are deposited at constant speeds when the first copper layer is firstly formed only in a via hole by leaving a first copper seed layer only in the via hole, and then the second copper layer is formed in a trench by forming a second copper seed layer in the trench.

Methods of forming interconnection lines in semiconductor devices

Methods of forming a metal line in a semiconductor device. A method includes: depositing a first etch stop layer, an interlayer insulating layer, a second etch stop layer, and a line insulating layer on a semiconductor substrate; forming a contact hole pattern on the line insulating layer; forming a contact hole by etching an exposed portion of the interlayer insulating layer using the contact hole pattern as a mask; forming a trench pattern on the line insulating layer; forming a trench by etching an exposed portion of the line insulating layer using the trench pattern as a mask; removing exposed portions of the first etch stop layer and the second etch stop layer after forming the contact hole and the trench; forming a first metal thin film within the contact hole; and forming a second metal thin film on the first metal thin film.

Methods of forming a metal line in a semiconductor device

Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a channel region formed in the semiconductor substrate and overlapping the gate, and LDD regions formed in the semiconductor substrate and at both sides of the gate, centering the gate. In addition, the example transistor includes source and drain regions formed under the LDD regions, offset regions formed in the semiconductor substrate and between the channel region and LDD regions, and gate spacers formed at both sidewalls of the gate.

Transistors and manufacturing methods thereof

The present disclosure relates to a flash memory including a common source line having a predetermined width formed on a semiconductor substrate, a common source in the semiconductor substrate below the common source line, and a couple of floating gates having a predetermined width formed on both outer side walls of the common source line. The flash memory may also include a couple of tunneling oxide layers formed between the floating gate and the common source line, and between the floating gate and the semiconductor substrate, a couple of dielectric layers formed on each of the couple of floating gates, and a couple of control gates formed on each of the couple of dielectric layers. Further, the flash memory may include a couple of drains formed in the semiconductor substrate by injecting impurity ions in using the control gate and the common source line as a mask.

Flash memories and methods of fabricating the same

Techiques for forming a silicon quantum dot, which can be applied to the formation of a semiconductor memory device, are disclosed. The techniques may include depositing a first dielectric layer on a semiconductor substrate, depositing a polysilicon layer on the first dielectric layer, forming a plurality of metal clusters on the polysilicon layer in regular distance, and etching the polysilicon layer using the plurality of metal clusters as a mask. As disclosed herein, it is possible to form the silicon quantum dots having the fineness and uniformity characteristic together with the single crystalline level characteristic.

Methods of forming silicon quantum dots and methods of fabricating semiconductor memory devices using the same

The disclosure provides methods of forming a silicon quantum dots for application in a semiconductor memory device. One example method includes sequentially forming a pad oxide film and a sacrificial insulation film on a silicon substrate; forming a wall layer by selectively etching the sacrificial insulation film; forming a spacer at the side wall of the wall layer; etching the silicon substrate as much as a predetermined thickness using the spacer as a mask, thereby forming a silicon pattern; forming a barrier film for burying the upper surface and the side surface of the silicon pattern; applying isotropic etching to the substrate using the barrier film as a mask; and oxidizing the isotropic etched substrate with thermal treatment.

Methods of forming silicon quantum dots and methods of fabricating semiconductor memory device using the same

A semiconductor device employing a PD-SOI substrate and a method of manufacturing the same are capable of minimizing a floating body effect. The semiconductor device employs a silicon layer over a buried insulating layer on a silicon wafer, isolating layers in the silicon layer in contact with the buried insulating layer, a body layer of a first conductivity type in the silicon layer between the isolating layers and having a trench, a gate insulating layer and a gate electrode in the trench of the body layer, a spacer on the sidewall of the gate electrode, LDD regions of a second conductivity type in the body layer on both sides of the gate electrode in contact with the buried insulating layer under the trench, and source and drain regions of the second conductivity type the body layer on both sides of the spacer in contact with the buried insulating layer.

Semiconductor device employing SOI substrate and method of manufacturing the same

An object of the present invention is to provide a MOS transistor of a new structure and a method of manufacturing the same that is capable of easily fabricating a high integration density device by overcoming photolithography limitations. The object of the present invention is accomplished by a MOS transistor, including a semiconductor substrate having a projection in which the width of an upper portion thereof is larger than that of a lower portion thereof; an isolating layer formed in the middle of substrate of the projection; first and second drain regions formed within the surface of the substrate of the projection; first and second source regions formed within the surface of the substrate on both sides of the projection; a gate insulating layer formed on the entire surface of the substrate; and first and second gates formed on the gate insulating layer on both sides of the substrate of the projection.

MOS transistor and method of manufacturing the same

A method of forming a MOS transistor is disclosed. An example method forms an insulating film and a first silicon layer on a semiconductor substrate in order. The example method forms an impurity region by injecting impurity ions into a predetermined region of the first silicon layer, forms a common source line by forming a second silicon layer on the impurity region, and then injecting impurity ions into the second silicon layer. The example method also forms a gate oxide over whole surfaces of the first silicon layer and the common source line, forms side walls made of insulating film on the gate oxide film positioned at sides of the common source line, forms drain regions by injecting impurity ions into the first silicon layer being positioned at a predetermined distance from the common source line, and forms gate electrodes on sides of the side walls.

MOS transistor and fabrication method thereof

As disclosed herein, a semiconductor device includes a gate and a silicon substrate having a field region and an active region. A gate dielectric layer formed on the upper surface of the active region of the silicon substrate and on a gate dielectric layer. The gate may include first and second sidewall dielectric layers sequentially formed on sidewalls of the gate, epitaxial silicon layers formed at both sides of the gate on the silicon substrate, first LDD regions formed in the silicon substrate below the second sidewall dielectric layers, second LDD regions formed at one sides of the first LDD regions below the epitaxial silicon layers, source/drain regions formed under the second LDD regions, and silicide layers formed on the gate and the source/drain regions.

Semiconductor devices and methods of fabricating the same

Methods for forming a contact hole in a semiconductor device are disclosed. A disclosed method is capable of preventing voids from being formed in a contact hole or a via hole. In particular, when a metal insulation film or an interlayer insulation film is selectively etched to form a contact hole or a via hole, a top edge of the contact hole or the via hole is rounded by using a plasma having spiral movement.

Methods of forming a contact hole in a semiconductor device

Semiconductor devices and methods of manufacturing the same are provided. A disclosed semiconductor device includes: a semiconductor substrate; a gate insulating layer on the active region of the semiconductor substrate; a gate on the gate insulating layer; LDD regions on opposite sides of the gate insulating layer and located in the semiconductor substrate; source/drain regions on the LDD regions; and silicide layers on the surfaces of the gate and the source/drain regions. The source/drain regions are formed by doping impurities in a silicon layer grown by a selective epitaxy.

Semiconductor devices and methods of manufacturing the same

In a method for fabricating a semiconductor device including a PIP capacitor and a MOS transistor, an isolator film is formed on a semiconductor substrate and then etched to expose an active region of the substrate. An epitaxial film is then formed by performing a selective epitaxial silicon growth process on the active region. A first polysilicon film, a dielectric film and a second polysilicon film are then sequentially formed. Next, an upper electrode is created by patterning the second polysilicon film. After a lower electrode and a gate electrode are formed by patterning the first polysilicon film, a source and a drain of a source/drain region are formed into the epitaxial film. Subsequently, after an interlayer insulation film is created on a resultant structure, contact holes are formed thereinto and contacts connected to the upper electrode, the lower electrode, the gate electrode and the source/drain region are formed.

Growing community of inventors

Bucheon, South Korea

Kwan-Ju Koh