Samsung Electronics Co., Ltd.

Kwan-jong Roh

Min-Joo Kim

Ja-hum Ku

Min-Chul Sun

Sun-Pil Youn

Sug-Woo Jung

Chul-sung Kim

Min-chul San

A method for fabricating a semiconductor device is provided using a nickel salicide process. The method includes forming a gate pattern and a source/drain region on a silicon substrate, forming a Ni-based metal layer for silicide on the silicon substrate where the gate pattern and the source/drain region are formed, and forming an N-rich titanium nitride layer on the Ni-based metal layer for silicide. Next, a thermal treatment is applied to the silicon substrate where the Ni-based metal layer for silicide and the N-rich titanium nitride layer are formed, thereby forming a nickel silicide on each of the gate pattern and the source/drain region. Then, the Ni-based metal layer for silicide and the N-rich titanium nitride layer are selectively removed to expose a top portion of a nickel silicide layer formed on the gate pattern and the source/drain region. Thus, as the N-rich titanium nitride layer is formed on the Ni-based metal layer for silicide, a silicide residue is prevented from forming a spacer and a field region formed of a field oxide layer.

Method for fabricating semiconductor device using a nickel salicide process

Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450&#xb0; C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSito suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.

Nickel alloy salicide transistor structure and method for manufacturing same

Methods of fabricating a semiconductor device having a MOS transistor with a strained channel are provided. The method includes forming a MOS transistor at a portion of a semiconductor substrate. The MOS transistor is formed to have source/drain regions spaced apart from each other and a gate electrode located over a channel region between the source/drain regions. A stress layer is formed on the semiconductor substrate having the MOS transistor. The stress layer is then annealed to convert a physical stress of the stress layer into a tensile stress or increase a tensile stress of the stress layer.

Methods of fabricating a semiconductor device having MOS transistor with strained channel

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Anyang, South Korea

Kwan-jong Roh