Hynix Semiconductor Inc.

Skhynix Inc.

Seoul National University

Kwan-Dong Kim

Suhwan Kim

Hae-Rang Choi

Kwang-Jin Na

Gi-Moon Hong

Joo-Hwan Cho

A memory module includes memory devices; data buffers suitable for receiving write data transferred from a memory controller and transmitting read data to the memory controller; a buffer control signal generation circuit suitable for generating buffer control signals for controlling the data buffers, by using a command transferred from the memory controller; a command delay circuit suitable for generating an effective command by delaying the command by a delay amount of the buffer control signal generation circuit in a read operation and a write operation; a data processing circuit suitable for processing write data transferred from the data buffers and transferring processed write data to the memory devices, and processing read data transferred from the memory devices and transferring processed read data to the data buffers, in response to the effective command; and a command buffer circuit suitable for transferring the effective command to the memory devices.

Memory module and memory system including the same

An integrated circuit may include a receiver suitable for comparing voltage levels of an external signal and a reference voltage with each other, and generating an internal signal, an adjustment code generation unit suitable for detecting a duty of the internal signal and generating an adjustment code of one or more bits, and a voltage adjustment unit suitable for adjusting the voltage level of the reference voltage in response to the adjustment code.

Integrated circuit

A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.

Phase-locked loop and integrated circuit chip including the same, and test system including the integrated circuit chip

A semiconductor memory device includes a first internal clock generation circuit configured to generate a first internal clock by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device, a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal, a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage, a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal, and a data output circuit configured to output a data in synchronization with the synchronization clock signal.

Clock generation circuit and semiconductor memory device employing the same

An integrated circuit includes a ring oscillator including delay cells having a delay value and configured to generate two or more periodic waves, a first phase controller configured to compare the phase of a first selected periodic wave to the phase of a reference wave and change the delay value of the delay cells from a first delay value to a second delay value based on a first comparison signal corresponding to a phase difference between the first selected periodic wave and the reference wave, and a second phase controller configured to compare the phase of a second selected periodic wave to the phase of the reference wave and restore the delay value of the delay cells from the second delay value to the first delay value based on a second comparison signal corresponding to a phase difference between the second selected periodic wave and the reference wave.

Integrated circuit with ring oscillator

A semiconductor memory device includes a clock period reflector configured to reflect time corresponding to period information of an internal clock signal to an input data signal, a data-clock converter configured to generate a synchronization clock signal having phases corresponding to an output signal of the clock period reflector, and a synchronization output unit configured to synchronize and output the input data signal in response to the synchronization clock signal.

Semiconductor memory device and operating method thereof

A semiconductor device includes a control voltage generating block configured to generate a control voltage corresponding to a phase difference between a reference clock signal and an internal clock signal, a control voltage restoring block configured to store the control voltage as a restoring voltage when entering into a low power mode and to supply the restoring voltage to a control voltage node when exiting from the low power mode, and an internal clock signal generating block configured to generate the internal clock signal corresponding to a voltage level of the control voltage.

Semiconductor device and operating method thereof

An integrated circuit includes an input unit and a voltage level detecting unit. The input unit is configured to output differential amplification signals corresponding to differential input signals in response to a voltage level detection signal. The voltage level detecting unit is configured to detect a voltage level of the differential amplification signals and output the voltage level detection signal.

A clock signal generation circuit includes a clock inversion unit inverting a reference clock signal and an internal clock signal to generate an inverted reference clock signal and an inverted internal clock signal, a first clock detection unit comparing the reference clock signal with the internal clock signal to output a first detection signal, a second clock detection unit comparing the inverted reference clock signal with the inverted internal clock signal to output a second detection signal, first and second charge pump units generating charge current or discharge current in response to the first second detection signals, respectively, a loop filter unit producing a control voltage signal having a voltage level corresponding to the charge currents or discharge currents, and an internal clock signal output unit producing the internal clock signal according to the control voltage signal.

Clock signal generation circuit

A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the internal clock, and to generate the feedback clock which is delayed in response to a control voltage based on the comparison; and a start voltage enable unit configured to receive an enable signal and to apply a start voltage as the control voltage in response to the enable signal.

Phase locked loop and method for operating the same

An integrated circuit includes a CML swing reference voltage generating unit, a CML bias control voltage generating unit and a CML buffering unit. The CML swing reference voltage generating unit determines a level of a CML swing reference voltage in response to a frequency setting code and a CML bias control voltage. The CML bias control voltage generating unit compares the level of the CML swing reference voltage with a level of a CML target reference voltage and determines a level of the CML bias control voltage based on the comparison result. The CML buffering unit generates a CML output signal swinging in a CML region by buffering an input signal and determines a swing level of the CML output signal on the basis of the level of the CML swing reference voltage in response to the frequency setting code and the CML bias control voltage.

Integrated circuit and method for operating the same

A phase locked loop can reduce a locking time, thereby efficiently reducing power in a locking operation. The phase locked loop includes a phase detector, a control voltage generator, a voltage controlled oscillator and a start-up driver. The phase detector detects a phase difference between a reference clock and a feedback clock to generate a detection signal corresponding to the detected phase difference. The control voltage generator generates a control voltage having a voltage level corresponding to the detection signal. The voltage controlled oscillator generates an internal clock having a frequency corresponding to a voltage level of the control voltage. The start-up driver drives a control voltage terminal to a predefined start-up level in response to a start-up level multiplex signal corresponding to a frequency of the reference clock prior to activation of the voltage controlled oscillator.

A semiconductor device is able to terminate internal transmission lines and including a pre-driving unit configured to generate a pull-up driving signal and a pull-down driving signal corresponding to an output data signal, and transfer the pull-up driving signal and the pull-down driving signal to a first transmission line and a second transmission line, respectively, a main driving unit configured to drive an output data in response to the pull-up driving signal and the pull-down driving signal transferred through the first transmission line and the second transmission line and a termination unit configured to be supplied with a termination voltage to terminate the first transmission line and the second transmission line.

Semiconductor device

Semiconductor device having multiple I/O modes. The device includes a data buffer configured to receive data; a strobe input buffer configured to receive a data strobe signal, a phase controller configured to shift a phase of the data strobe signal by different numbers of degrees, including 0 degrees, according to input modes and a data detector configured to detect the data in response to the data strobe signal output from the phase controller.

Growing community of inventors

Gyeonggi-do, South Korea

Kwan-Dong Kim