Hong Kong Applied Science and Technology Research Institute Company, Limited

Kwai Chi Chan

Ho Ming (Karen) Wan

Yat To (William) Wong

Kwok Kuen (David) Kwong

Kam Chuen Wan

Kwok Kuen David Kwong

Yat To William Wong

Ho Ming Karen Wan

Tin Ho (Andy) Wu

Andrea Baschirotto

Yunlong Li

Hok Mo Yau

Lee L Yang

Xiao Fei Kuang

Tin Ho Andy Wu

A correcting asynchronous Successive-Approximation Register (SAR) analog-to-digital converter (ADC) detects and corrects metastability errors. An analog signal is synchronously sampled by a system clock, but data bits are converted asynchronously. A valid detector compares true and complement outputs of a comparator that compares the sampled voltage to a DAC voltage generated from digital test value from the SAR. Once the true and complement outputs diverge past logic thresholds, the valid detector activates a VALID signal indicating that comparison is completed. The compare result is then latched in as a data bit and the SAR advances to the next test value. Once all bits have been converted, an End-of-Conversion (EOC) is signaled. If the EOC does not occur by the end of the system clock, a metastability error is detected. The current bit that never finished comparison is forced high and all other unconverted bits are forced low.

Asynchronous successive-approximation-register analog-to-digital converter (SAR ADC) in synchronized system

A Programmable-Gain Amplifier (PGA) has a digital value that programmably adjusts the gain of the analog amplifier. A variable capacitor has several switched sub-capacitors that are enabled by the digital value. Enabled sub-capacitors are switched between a sampled input and a virtual ground on one terminal, and connect to a summing node on the other terminal. The summing node connects to the inverting input of an op amp either through a switch or through a double-sampling capacitor that stores an offset. A feedback capacitor is in parallel with a sampling capacitor during a second clock phase when direct-charge transfer occurs, reducing power consumption of the amplifier. The feedback capacitor samples the sampled input during the first clock phase. The PGA gain is proportional to the sum of capacitances of enabled sub-capacitors. The gain can be adjusted for sensor inputs to an Analog Front-End (AFE), such as for an electro-cardiogram (ECG).

Digitally-programmable gain amplifier with direct-charge transfer and offset cancellation

A transistor-based full-wave bridge rectifier is suitable for low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a bridge across the A.C. inputs to produce an internal power voltage. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors with voltages boosted higher than the peak A.C. voltage. Four diode-connected transistors are connected in parallel with the four p-channel bridge transistors to conduct during initial start-up before the comparator and boost drivers operate. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow. The transistor bridge can be integrated onto system chips.

Self-starting transistor-only full-wave rectifier for on-chip AC-DC conversion

An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.

Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge

A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.

Configurable cascading sigma delta analog-to digital converter (ADC) for adjusting power and performance

A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.

Charge compensation calibration for high resolution data converter

A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.

Ultra low voltage multi-stage high-speed CMOS comparator with autozeroing

A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.

Bi-directional trimming methods and circuits for a precise band-gap reference

An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.

Multi-stage comparator with offset canceling capacitor across secondary differential inputs for high-speed low-gain compare and high-gain auto-zeroing

A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.

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Kwai Chi Chan