Apple Inc.

Kutty Banerjee

Tatsuya Iwamoto

Pratik Chandresh Shah

Rohan Sanjeev Patil

Michael Imbrogno

Benjamin Bowman

Terence M Potter

Gokhan Avkarogullari

Fergus W MacGarry

David E Roberts

Benjiman L Goodman

Francesco Rossi

Jason P Jane

Eric O Sunalp

Subodh Asthana

Kyle J Haughey

Disclosed techniques relate to circuitry configured to aggregate and report usage information in a distributed processor (e.g., a GPU). In some embodiments, graphics processor circuitry that includes at least first and second portions that are respectively configured to execute sets of graphics work. First utilization circuitry may track execution time for sets of graphics work on the first portion of the graphics processor circuitry and second utilization circuitry may track execution time for sets of graphics work on the second portion of the graphics processor circuitry. Command queue circuitry may store multiple different command queues. Control circuitry may access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, where for a given command queue, the aggregated utilization data indicates respective utilization of the first and second portions of the graphics processor circuitry. The control circuitry may provide the aggregated per-command-queue utilization data in software-accessible registers.

Quality of service techniques in distributed graphics processor

Disclosed techniques relate to distributing graphics work based on priority. In some embodiments, circuitry implements a plurality of tracking slots for sets of graphics work. A set of graphics processor sub-units may each implement multiple distributed hardware slots. Control circuitry may attempt to assign a first set of graphics work having a first priority to a graphics processor sub-unit that is currently executing graphics work having an equal or higher priority than the first priority, where the first set of graphics work is from a first tracking slot. The control circuitry may, in response to a failure of the attempt, generate a signal to graphics software that indicates the failure, wherein the signal indicates the first tracking slot. Disclosed techniques may reduce or avoid problems relating to higher priority work being scheduled behind lower priority work.

Priority inversion mitigation techniques

One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.

Power aware translation lookaside buffer invalidation optimization

In general, embodiments are disclosed herein for tracking and allocating graphics hardware resources. In one embodiment, a software and/or firmware process constructs a cross-application command queue utilization table based on one or more specified command queue quality of service (QoS) settings, in order to track the target and current utilization rates of each command queue on the graphics hardware over a given frame and to load work onto the graphics hardware in accordance with the utilization table. Based on the constructed utilization table for a given frame, any command queues that have exceed their respective target utilization value may be moved to an 'inactive' status for the duration of the current frame. For any command queues that remain in an 'active' status for the current frame, work from those command queues may be loaded on to slots of the appropriate data masters of the graphics hardware in any desired order.

Normalizing target utilization rates of a cross-application table of concurrently executing applications to schedule work on a command queue of a graphics processors

A first command is fetched for execution on a GPU. Dependency information for the first command, which indicates a number of parent commands that the first command depends on, is determined. The first command is inserted into an execution graph based on the dependency information. The execution graph defines an order of execution for plural commands including the first command. The number of parent commands are configured to be executed on the GPU before executing the first command. A wait count for the first command, which indicates the number of parent commands of the first command, is determined based on the execution graph. The first command is inserted into cache memory in response to determining that the wait count for the first command is zero or that each of the number of parent commands the first command depends on has already been inserted into the cache memory.

Execution graph acceleration

Translation lookaside buffer invalidation for merged invalidation requests across power boundaries

Systems, methods, and computer readable media to manage power for a graphics processor are described. When the power management component determines the graphics processor is idle when processing a current frame by the graphics processor, the power management component predicts an idle period for the graphics processor based on the work history. The power management component obtains a first latency value indicative of a power on time period and a second latency value indicative of a power off time period for a graphics processor component, such as graphics processor hardware. The power management component provides power instructions to transition the graphics processor component to the power off state based on a determination that a combined latency value of the first latency value and the second latency value is less than the idle period.

Proactive power management of a graphics processor

The embodiments disclosed herein relate to the field of graphics processing and, without limitation, to techniques to enable efficient sharing of a graphics processing unit (GPU) between user interface (UI) graphics operations and intense compute operations. In certain embodiments, intense compute operations, such as long accumulations, are divided into multiple pieces. A scheduler is added to force context switching if an intense compute operation is blocking timely execution of a UI graphics operation. The division of the intense compute operation is tuned so that the GPU compute queue can drain during approximately the same time required to perform a context switch on the GPU.

System and method to share GPU resources

Systems, methods, and computer readable media to improve task switching operations in a graphics processing unit (GPU) are described. As disclosed herein, the clock rate (and voltages) of a GPU's operating environment may be altered so that a low priority task may be rapidly run to a task switch boundary (or completion) so that a higher priority task may begin execution. In some embodiments, only the GPU's operating clock (and voltage) is increased during the task switch operation. In other embodiments, the clock rate (voltages) of supporting components may also be increased. For example, the operating clock for the GPU's supporting memory, memory controller or memory fabric may also be increased. Once the lower priority task has been swapped out, one or more of the clocks (and voltages) increased during the switch operation could be subsequently decreased, though not necessarily to their pre-switch rates.

Fast GPU context switch

In general, embodiments are disclosed for tracking and allocating graphics processor hardware resources. More particularly, a graphics hardware resource allocation system is able to generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters. The graphics hardware resource allocation system designate, based on the priority list, a first data master with a higher priority to submit work to the graphics processor compared to a second data master. The graphics hardware resource allocation system determines a stall counter value for the data master and generates a notification to pause work for the second data master based on the stall counter value.

Graphics hardware driven pause for quality of service adjustment

One disclosed embodiment includes a method of scheduling graphics commands for processing. A plurality of micro-commands is generated based on one or more graphics commands obtained from a central processing unit. The dependency between the one or more graphics commands is then determined and an execution graph is generated based on the determined dependency. Each micro-command in the execution graph is connected by an edge to the other micro-commands that it depends on. A wait count is defined for each micro-command of the execution graph, where the wait count indicates the number of micro-commands that the each particular micro-command depends on. One or more micro-commands with a wait count of zero are transmitted to a ready queue for processing.

Low latency firmware command selection using a directed acyclic graph

In general, techniques are disclosed for tracking and allocating graphics processor hardware over specified periods of time. More particularly, hardware sensors may be used to determine the utilization of graphics processor hardware after each of a number of specified intervals (referred to as 'sample intervals'). The utilization values so captured may be combined after a first number of sample intervals (the combined interval referred to as an 'epoch interval') and used to determine a normalized utilization of the graphic processor's hardware resources. Normalized epoch utilization values have been adjusted to account for resources used by concurrently executing processes. In some embodiments, a lower priority process that obtains and fails to release resources that should be allocated to one or more higher priority processes may be detected, paused, and its hardware resources given to the higher priority processes.

GPU resource priorities based on hardware utilization

Embodiments are directed toward systems and methods for scheduling resources of a graphics processing unit that determine, for a number of applications having commands to be issued to the GPU, a static priority level and a dynamic priority level of each application, work iteratively across static priority levels until a resource budget of the GPU is consumed, and starting with a highest static priority identify the applications in a present static priority level, assign a processing budget of the GPU to each of the applications in the present static priority level according to their dynamic priority levels, and admit to a queue commands from the applications in the present static priority level according to their processing budgets, and release the queue to the GPU.

Growing community of inventors

San Jose, CA, United States of America

Kutty Banerjee