Xilinx, Inc.

Kushagra Sharma

Darren S Jue

Tao Yu

Chandrasekhar S Thyamagondlu

Ravi S Sunkavalli

Akhil Krishnan

Tuan Van-Dinh

A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.

Multi-host direct memory access system for integrated circuits

A direct memory access (DMA) system can include a memory configured to store a plurality of host profiles, a plurality of interfaces, wherein two or more of the plurality of interfaces correspond to different ones of a plurality of host processors, and a plurality of data engines coupled to the plurality of interfaces. The plurality of data engines are independently configurable to access different ones of the plurality of interfaces for different flows of a DMA operation based on the plurality of host profiles.

A memory circuit is configured for storage of completion queues. Each completion queue can store completion descriptors associated with transfers of data from interrupt source circuits to the memory circuit. A direct memory access circuit provides access to the memory circuit for the interrupt source circuits. An interrupt engine issues interrupt messages for processing the completion descriptors in the completion queues in response to satisfaction of a set of trigger conditions specified in an active interrupt moderation mode. The active interrupt moderation mode is one of multiple available interrupt moderation modes. The interrupt engine bypasses issuing interrupt messages in response to the set of trigger conditions of the active interrupt moderation mode not being satisfied.

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Santa Clara, CA, United States of America

Kushagra Sharma