Motorola Corporation

Freescale Semiconductor,inc.

Applied Materials, Inc.

Motorola Mobility LLC

Kurt W Eisenbeiser

Ravindranath Droopad

Jenn-Hwa Huang

Jamal Ramdani

Yang Wang

Zhiyi Jimmy Yu

William J Ooms

Ellen Lan

Yu Wang

Lyndee L Hilt

Bich-Yen Nguyen

Ramamoorthy Ramesh

Vijay K Nair

Ramkumar Krishnan

Byung-Sung Kwak

Jeffrey M Finder

Nada El-Zein

Ramoothy Ramesh

Jerald A Hallmark

Jun J Wang

William J Dauksher

Byung Sung Kwak

Nety M Krishna

Chowdary Ramesh Koripella

Barbara M Foley

Majid M Hashemi

Jon J Candelaria

Alexander A Demkov

Benjamin W Gable

Sang-In Han

Danny L Thompson

David B Rhine

Bing Lu

Jon Candelaria

Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.

Method for high volume manufacturing of thin film batteries

A method is provided for fabricating an integrated micro fuel cell that derives power from a three-dimensional fuel/oxidant interchange having increased surface area and that is positioned on a second substrate that may be either porous or flexible with gas access holes, thereby avoiding precise alignment requirements of the openings providing fuel thereto. The method comprises forming on a first substrate, a plurality of pedestals including an anode and a cathode each comprising a porous metal; positioning an electrolyte between the anode and the cathode; and forming first metal contacts on the anode and cathode. The first substrate is removed and a second substrate is positioned against the fuel cell wherein the first metal contacts are selectively positioned to make electrical contact with second metal contacts on the second substrate.

Method for forming a micro fuel cell

A monolithically integrated lithium thin film battery () provides increased areal capacity on a single level (without stacking of multiple cells). The Lithium thin film battery () comprises a substrate () having a surface () textured to comprise a plurality of openings () having sides () angled between 10 and 80 degrees to the surface (). A current collector () and a cathode () are formed on the substrate () and within the openings (). An electrolyte () comprising lithium phosphorous oxynitride is formed by physical vapor deposition on the cathode (), thereby providing a layer on the surface of the cathode () and within the openings () of the cathode having substantially the same thickness. An anode () and a capping layer () are then formed on the electrolyte ().

Thin film battery having textured layer

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Heterojunction tunneling diodes and process for fabricating same

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same

Circuit () has a dual layer gate dielectric () formed over a semiconductor substrate (). The gate dielectric includes an amorphous layer () and a monocrystalline layer (). The monocrystalline layer typically has a higher dielectric constant than the amorphous layer.

Semiconductor device and method

The present invention provides a method of fabricating a silicon fin useful in preparing FinFET type semiconductor structures. The method is particularly useful for creating fins with a width and smoothness appropriate for sub-50 nm type gates. The method begins with a silicon fin prepared by lithographic means from an SOI type structure such that the fin is larger in dimension, particularly width, than is desired in the final fin. If desired the silicon fin can include a nitride cap. A conformal diffusion layer, such as of silicon dioxide, is then deposited onto the fin and silicon dioxide substrate. A PECVD deposition using TEOS gas is one method to deposit the diffusion layer. The coated fin is then heated and exposed to oxygen. The oxygen diffuses through the diffusion layer and converts a portion of the silicon material to silicon dioxide. This oxidation continues until a desired amount of silicon material is converted to SiOsuch that the remaining silicon has the desired dimensions. The silicon fin is then exposed through wet etching steps that remove the silicon dioxide coating.

Method of fabricating three dimensional gate structure using oxygen diffusion

A semiconductor device includes a continuous doped substrate with a surface, a sulfur-based dielectric material layer positioned on the surface of the continuous doped substrate, a dielectric material layer positioned on the sulfur-based dielectric material layer, and a gate contact region positioned on the sulfur-based dielectric material layer. The continuous doped substrate includes silicon (Si) and the sulfur-based dielectric material includes a transition metal sulfide such as strontium zirconium sulfur (SrZrS), barium zirconium sulfur (BaZrS), strontium hafnium sulfur (SrHfS), barium hafnium sulfur (BaHfS), or the like. Further, the gate contact region includes a layer of one of strontium titanium sulfur (SrTiS), barium titanium sulfur (BaTiS), or the like positioned adjacent to the dielectric material layer.

Semiconductor device structures which utilize metal sulfides

A high quality epitaxial layer of monocrystalline Pb(Zr,Ti)O can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.

Microelectronic piezoelectric structure and method of forming the same

High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. A monocrystalline layer is then formed over the accommodating buffer layer, such that a lattice constant of the monocrystalline layer substantially matches the lattice constant of a subsequently grown monocrystalline film.

Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. To further relieve strain in the accommodating buffer layer, at least a portion of the accommodating buffer layer is exposed to a laser anneal process to cause the accommodating buffer layer to become amorphous, providing a true compliant substrate for subsequent layer growth.

Semiconductor structure including a partially annealed layer and method of forming the same

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. These semiconductor materials have applications involving communications with high frequency signals including intelligent transportation systems such as automobile radar systems, smart cruise control systems, collision avoidance systems, and automotive navigation systems; and electronic payment systems that use microwave or RF signals such as electronic toll payment for various transportation systems including train fares, and toll roads, parking structures, and toll bridges for automobiles.

Semiconductor structure for use with high-frequency signals

High quality epitaxial layers of monocrystalline materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer ( ) on a silicon wafer ( ). The accommodating buffer layer ( ) is a layer of monocrystalline material spaced apart from the silicon wafer ( ) by an amorphous interface layer ( ) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Utilizing this technique permits the fabrication of thin film pyroelectric devices ( ) on a monocrystalline silicon substrate.

Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same

High quality epitaxial layers of piezoelectric material materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Acoustic wave device and process for forming the same

A high quality epitaxial layer of monocrystalline Pb(Mg,Nb)O &mdash;PbTiO or Pb(Mg Nb )O &mdash;PbTiO can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.

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Tempe, AZ, United States of America

Kurt W Eisenbeiser