Marvellworld Trade Ltd.

Marvell International Limited

Kurt Thomas Boden

Jakob Carlström

Gil Levy

Carmi Arad

Gunnar Nordmark

Par Westlund

Lars-Olof B Svensson

Mikael Karpberg

A meter module for use in a network device comprises conformance circuitry configured to: access a first memory device storing a conformance indicator that indicates whether a permitted rate of packet traffic has been exceeded, and classify packets received at the network device based at least in part on the conformance indicator. Sampling circuitry is configured to, responsively to the conformance circuitry classifying the packets: sample events associated with at least some of the received packets, and generate indicators of the sampled events. Update circuitry is configured to: access a second memory device, slower than the first memory, to update a number of tokens stored in the second memory device, and access the first memory device to update the conformance indicator when the updated number of tokens indicates that the permitted rate of packet traffic has been exceeded.

Time efficient counters and meters architecture

A network device includes a plurality of interfaces configured to receive, from a network, packets to be processed by the network device. A load determination circuit of the network device is configured to determine whether a packet traffic load of the network device is above a traffic load threshold, and a dual-mode counter module is configured to (i) determine a count of quanta associated with the received packets using a first counting mode in response to the load determination unit determining that the packet traffic load is above the traffic load threshold, and (ii) determine a count of quanta associated with the received packets using a second counting mode, different than the first counting mode, in response to the load determination unit determining that the packet traffic load is not above the traffic load threshold.

A system including a receiver and a processing pipeline. The receiver is configured to generate a data block by encapsulating a data packet in a header portion and a tail portion that do not include valid information bits. The processing pipeline is configured to, in a first processing stage, store the data block, and store, separately from the data block, additional information associated with the data block. The processing pipeline is further configured to, without modifying a length of the data block, either add bits to the header portion or the tail portion to increase the length of the data packet or subtract bits from the data packet to decrease the length of the data packet, and modify the additional information in accordance with the bits added to the header portion or the tail portion or the bits subtracted from the data packet.

System and method for modifying, in a processing pipeline, a length of a data packet in a data block without modifying a length of the data block

A network processing device comprising a plurality of programmable processors coupled together to perform a set of packet processing operations to process a packet received by the network processing device. Ones of the programmable processors being configured to perform a respective subset of the set of packet processing operations with a respective portion of a packet context such that respective programmable processors receives a portion of the packet context, that is less than a full packet context for performing the packet processing operations. The portion of a packet context being dimensioned to perform the respective subset of the packet processing operations.

Dynamic processing context

A packet processing device has a plurality of processing stages, including a first processing stage and a second processing stage arranged as a packet processing pipeline. The first processing stage and the second processing stage each have a respective processor configured to process a packet of a packet stream and a respective resource manager having a respective local resource lock corresponding to a remote resource. The respective processor requests the respective resource manager to allocate the remote resource. The respective resource manager responds to the request to allocate the remote resource by locking the remote resource with the respective local resource lock and allocating the remote resource. The respective processor implements a packet processing operation associated with the allocated remote resource.

Semaphore soft and hard hybrid architecture

A network device that processes a stream of packets has an ingress front end. The ingress front end determines whether the packets are handled in a bounded latency path or in a best-effort path. The bounded latency path packets are granted a resource with a higher priority than the best-effort path packets. As the packets are processed through a number of processing stages, with processing engines, the bounded latency packets are processed within a period of time corresponding to a guaranteed rate. Resources are granted to the best-effort path packets only when the processing engines determine that the resource grant will not impact the latency bounds with respect to the first packets.

Hybrid dataflow processor

A network processor includes an arbitration device, a processing device, and a pipeline. The arbitration device receives a first packet and a second packet. The second packet includes a first control message. The pipeline includes access devices, where the access devices include first and second access devices. The pipeline, based on a clock signal, forwards the first and second packets between successive ones of the access devices. The arbitration device: sets a timer based on at least one of (i) an amount of time for data to travel between the first and second access devices, or (ii) a number of pipeline stages between the first and second access devices; adjusts a variable based on (i) the clock signal, and (ii) transmission of the first packet from the arbitration device to the pipeline; and based on the timer and the variable, schedules transmission of the second packet through the pipeline.

Method and apparatus for scheduling packets for transmission in a network processor having a programmable pipeline

Systems and methods are provided for counting a number of received packets and a number of bytes contained in the received packets. A system includes a first memory disposed in an integrated circuit, the first memory being configured as a first combination counter having a first set of bits for storing a subtotal of received packets, and a second set of bits for storing a subtotal of bytes contained in the received packets. A second memory is external to the integrated circuit. The second memory is configured to store a total number of received packets and a total number of bytes contained in the received packets. Update circuitry is configured to update the total number of packets stored in the second whenever either of the first set of bits or the second set of bits overflows in the first memory.

Method and apparatus for internal/external memory packet and byte counting

The disclosed embodiments relate to a packet-processing system. This system includes an input which is configured to receive packets, wherein the packets include control-message (CM) packets and traffic packets. It also includes a pipeline to process the packets, wherein the pipeline includes access points for accessing an engine which services requests for packets, wherein CM packets and traffic packets access the engine through different access points. The system additionally includes an arbiter to schedule packets entering the pipeline. While scheduling the packets, the arbiter is configured to account for empty slots in the pipeline to ensure that when CM packets and traffic packets initiate accesses to the engine through different access points, the accesses do not cause an overflow at an input queue for the engine.

Growing community of inventors

Strangnas, Sweden

Kurt Thomas Boden