Advanced Micro Devices Corporation

Kurt Taylor

Todd P Lukanc

Amit P Marathe

Eugene Zhao

Akram Ali Salman

Richard C Blish

Hyeon-Seag Kim

Stephen G Beebe

Wiley Eugene Hill

Chern-Jiann Lee

David C Greenlaw

Huade Walter Yao

Rolf Geilenkeuser

Xuejun Zhao

John Zhang

Jay Chan

Joerg-Oliver Weidner

Rithy Hang

A method for efficiently and accurately measuring a maximum Vcalculation or failure rate and lifetime projection for microprocessors and other semiconductor products analytically scales low voltages applied to thinner oxides to thicker oxides. The expanded voltage window that is closer to the use voltage is obtained thereby to provide accurate voltage acceleration factors and max Vextraction.

Method for determining projected lifetime of semiconductor devices with analytical extension of stress voltage window by scaling of oxide thickness

The present invention is generally directed to various methods for determining the reliability of dielectric layers. In one illustrative embodiment, the method comprises providing a device having a dielectric layer, applying a plurality of constant voltage pulses to the device and measuring a current through the dielectric layer after one or more of the constant voltage pulses has been applied.

Method for determining the reliability of dielectric layers

For determining a failure characteristic of a semiconductor device, a leakage current characteristic is measured for the semiconductor device to determine a plurality of stress bias zones. A respective set of parameters that define a respective failure characteristic of the semiconductor device is determined for each of the stress bias zones such that the failure characteristic is accurately determined for a wide range of operating voltages.

Determination of device failure characteristic

Aspects for increasing accuracy in predicting HCI degradation in semiconductor devices are described. The aspects include a gated ring oscillator structure utilized to perform HCI degradation testing with controlling of the gated ring oscillator structure to isolate voltage acceleration degradation from frequency degradation directly during the HCI degradation testing. Further included is a plurality of ring oscillators coupled in series, and first and second control logic for the plurality of ring oscillators for enabling selection of gated operation of the plurality of ring oscillators, wherein each ring oscillator performs a same number of transitions to allow an accurate assessment of HCI degradation based solely on voltage acceleration.

Structure and method for increasing accuracy in predicting hot carrier injection (HCI) degradation in semiconductor devices

A testing system and method of operation therefor is provided including a test fixture for electrical testing above a thermal threshold temperature of a low dielectric constant material and having a test-chip-die-sized enclosed volume. The test fixture has an electrical connection from the enclosed volume to the outside thereof and a removable lid for sealing the enclosed volume in the test fixture.

Testing system and method of operation therefor including a test fixture for electrical testing of semiconductor chips above a thermal threshold temperature of an interlayer dielectric material

A method for making frontside contact to a substrate through an SOI structure thereon is provided. An etching step is undertaken to form a trench in the SOI structure so as to expose and define a rug surface of the substrate. Then, a thin insulating layer, for example SiO , is formed over the exposed surface of the substrate, this insulating layer being irregular because of its formation over the relatively rough etched surface. Contact material is provided in the trench, and electrical potential is applied across the contact and substrate sufficient to increase the conductivity of the insulating layer, i.e., to break down the insulating layer. Nitrogen may be implanted into the exposed surface of the substrate to slow subsequent growth of the insulating layer, resulting in an even thinner insulating layer, i.e., one even less resistant to breakdown upon application of electrical potential thereacross. If the insulating layer thereon is sufficiently thin or irregular, ohmic contact may be achieved between the contact and substrate without the application of such electrical potential. In yet another embodiment, prior to formation of the insulating layer, the exposed surface of the substrate and wall of the trench are fabricated such that meet at an abrp angle. Insulating material formed in ths area is of poor quality, readily lending itself to breakdown upon application of electrical potential across the contact material and substrate.

Method of providing a frontside contact to a substrate of SOI device

A variable design tool utilizes memory units to determine at which point a design rule fails. The variable design tool can provide a bit map indicating the points of failures for particular rules. The bit map can also be utilized to determine misalignment errors. The memory cells, typically SRAM units are arranged in 4&times;4 matrices which are arranged in four 16&times;16 matrices.

Variable design rule tool

A metal edge seal ring is formed in a trench made up of a large number of short, connected legs in perpendicular relation. Metal is deposited in the trench, and because the metal is comprised of many short segments rather than several long, straight sections, the subsequent chemical-mechanical polishing step does not cause significant cupping of the metal in the trench.

Edge seal ring for copper damascene process and method for fabrication thereof

A method for making frontside contact to a substrate through an SOI structure thereon is provided. An etching step is undertaken to form a trench in the SOI structure so as to expose and define a rough surface of the substrate. Then, a thin insulating layer, for example SiO , is formed over the exposed surface of the substrate, this insulating layer being irregular because of its formation over the relatively rough etched surface. Contact material is provided in the trench, and electrical potential is applied across the contact and substrate sufficient to increase the conductivity of the insulating layer, i.e., to break down the insulating layer. Nitrogen may be implanted into the exposed surface of the substrate to slow subsequent growth of the insulating layer, resulting in an even thinner insulating layer, i.e., one even less resistant to breakdown upon application of electrical potential thereacross. If the insulating layer thereon is sufficiently thin or irregular, ohmic contact may be achieved between the contact and substrate without the application of such electrical potential. In yet another embodiment, prior to formation of the insulating layer, the exposed surface of the substrate and wall of the trench are fabricated such that meet at an abrupt angle. Insulating material formed in this area is of poor quality, readily lending itself to breakdown upon application of electrical potential across the contact material and substrate.

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San Jose, CA, United States of America

Kurt Taylor