Northrop Grumman Systems Corporation

Kurt Pleim

Alexander Louis Braun

Max Earl Nielsen

Haitao O Dai

Charles Ryan Wallace

Daniel George Dosch

Joel D Strand

Robert L Miller

Micah John Atman Stoutimore

Andrew Hostetler Miklich

Cody James Ballard

Sean Ashley Lindsay

One example includes a superconducting serial-to-parallel converter system. The system includes a plurality of serial-input-parallel-output (SIPO) cells arranged in a sequence between a first SIPO cell and a last SIPO cell. Each of the SIPO cells is configured to convert a plurality of serial superconducting bits of a serial data stream into a set of parallel superconducting bits in response to an enable pulse. The enable pulse is provided through the sequence of SIPO cells from the first SIPO cell to the last SIPO cell based on the clock signal. The serial data stream is provided through the sequence of the SIPO cells from the last SIPO cell to the first SIPO cell based on a clock signal.

Superconducting serial-to-parallel converter system

An output-amplifier-based reciprocal quantum logic (RQL) bias-level sensor is used to measure and/or calibrate bias parameters of AC and/or DC bias signals provided to RQL circuitry. The bias signals can include an output amplifier output bias current. The bias-level sensor includes a stack of DC SQUIDs that are supplied their inputs from outputs of respective Josephson transmission lines (JTLs) to which the SQUIDs are transformer-coupled. Staging relative strengths of the bias taps of the JTLs, or the critical currents of the Josephson junctions in the DC SQUIDs, allows an output voltage signal of the bias-level sensor to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range. The outputs of two such bias-level sensors driven by I and Q clocks can be compared to adjust AC bias amplitudes of the clocks. Relative clock phase can be similarly adjusted.

Squid stack pulse height bias-level sensor for reciprocal quantum logic

Pulse-generator-based reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors include pulse generators having strengthened or weakened bias taps (transformer couplings to RQL AC clock resonators or DC bias lines) as compared to bias taps of Josephson transmission lines in the operational RQL circuitry, or Josephson junctions (JJs) with larger or smaller critical currents as compared to JJs in the operational RQL circuitry. Pulse generators with weakened bias taps or larger JJs can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. The bias-level sensors can be staged by relative strength to indicate whether a provided bias value is an improvement when varied over a range.

Pulse-generator-based bias-level sensors for reciprocal quantum logic

Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.

Phase-mode bit-addressable sensing register

One example includes a flux switch system. The system includes an input stage configured to provide an interrogation pulse. The system also includes a plurality of flux loops configured to receive an input current. Each of the flux loops includes a Josephson junction configured to trigger to generate an output pulse in response to a first polarity of the input current and to not trigger to generate no output pulse in response to a second polarity of the input current opposite the first polarity. The system further includes an output stage configured to propagate the output pulse to an output of the flux switch system.

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Halethorpe, MD, United States of America

Kurt Pleim