International Business Machines Corporation

Kurt Paul Szabo

George Henry Ahrens, Jr

Mike Conrad Duron

Robert Allan Faust

Algirdas J Gruodis

Forrest Clifton Gray

Charles Andrew McLaughlin

Dale E Hoffman

Jayeshkumar M Patel

Craig Henry Shempert

John C Kennel

Michael L Combs

Charles A Puntar

Piyushkumar C Patel

In accordance with the method and system of the present invention, a local processor utilizes registers arranged in a fault/mask/cache fashion for environmental control and sensing within a data processing system. The local processor continuously reads input data from a variety of environmental sensors in order to determine if a threshold level has been reached and a fault condition exists. Cache registers allow the local processor to store/pass detailed sensor information to system firmware within system processor(s). The local processor sets a fault bit within a fault register designed to cause an interrupt to the system level firmware if any of its bits are non-zero, indicating that a fault condition has occurred. A mask register is designed to allow the interaction of both the local processor and system processor(s) when an interrupt is being serviced and help keeps track of which interrupts are being serviced and which are yet to be serviced in the case of multiple interrupt sources. The system firmware will service the interrupt and set the mask bit. The action will signal the local processor that the system has acknowledged the interrupt and will take the appropriate action. The local processor may now post another fault, exactly like the first fault, by clearing the mask bit and causing a subsequent interrupt to the system. The fault, mask, cache, and both local and system processor(s) work together to provide a positive interlock for synchronizing their actions with each other.

Method and system for environmental sensing and control within a computer system

A method and implementing apparatus is provided which include a plurality of perceptible indicia devices which are mounted on an I/O drawer of a computer system server equipment rack. In the exemplary embodiment, the indicia devices include a light-emitting diode in combination with an alphanumeric display device. Various states of a system initialization process are indicated by different combinations of possible states of the LED and the display device such that the sequencing of a system initialization process can be traced by visual inspection of the status of the perceptible indicia devices.

Cues for status information

A data processing system includes a plurality of components, a power control network, processing resources, and a memory that contains initialization firmware. At system startup, the power control network initiates supply of power to the plurality of components and collects information regarding which components are supplied power. In addition, the initialization firmware initializes the plurality of components to establish a configuration. If an ambiguity in the configuration arises, the initialization firmware resolves the ambiguity utilizing the information collected by the power control network.

Method and system for configuring resources in a data processing system utilizing system power control information

A multitude of devices coupled to a processor are each given a location code, which is then displayed in proximity to each of the devices. Then, when the processor indicates an error within a particular device, the service person can easily find which device has the error by the displayed location code associated with the device.

System diagnostic location codes

A parallel operation linear feedback shift-register (LFSR) that generates random test patterns or creates a signature that represents the response of a device under test at ultra high speed using low speed components and/or a slow rate clock. The apparatus is comprised of: a register connected to an external clock, and a plurality of combinatorial logic networks sequentially connected, the last of which drives the register which in turn feeds back into the first of the combinatorial logic networks. Each of the combinatorial networks provides a pseudo-random pattern which are then outputted in parallel, thereby creating a high speed data flow. By providing additional data inputs to the combinatorial networks, the pseudo-random patterns become the signature of the input data.

Parallel operation linear feedback shift register

Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2.sup.M or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin. The test system also includes test pin signal receiving circuitry [26] for coupling to the test pin for receiving an electrical signal therefrom. Other predetermined ones of the control bits are coupled to the receiving circuitry for specifying, for each of the test cycles, at least one operating characteristic associated with the receiving circuitry.

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Austin, TX, United States of America

Kurt Paul Szabo