Intermolecular, Inc.

Other

Kurt Pang

Frank Greer

Yun Yu Wang

Chi-I Lang

Ratsamee Limdulpaiboon

Sandip Niyogi

Edwin Adhiprakasha

J Watanabe

Andrew Steinbach

Tony Bonetti

Provided are superconducting tunnel junctions, such as Josephson tunnel junctions, and a method of fabricating thereof. A junction includes an insulator disposed between two superconductors. The junction may also include one or two interface layers, with each interface layer disposed between the insulator and one of the superconductors. The interface layer is configured to prevent oxygen from entering the adjacent superconductor during fabrication and operation of the junction. Furthermore, the interface layer may protect the insulator from the environment during handling and processing of the junction, thereby allowing vacuum breaks after the interface layer is formed as well as new integration schemes, such as depositing a dielectric layer and forming a trench in the dielectric layer for the second superconductor. In some embodiments, the junction may be annealed during its fabrication to move oxygen from the superconductors and/or from the insulator into the one or two interface layers.

Superconducting junctions

A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO, and (4) in-situ deposition of the dielectric overlayer to prevent uncontrolled regrowth of native oxide. The monolayer of GeOpromotes uniform nucleation of the dielectric overlayer, but it too thin to appreciably impact the effective oxide thickness of the dielectric overlayer.

Nucleation interface for high-k layer on germanium

A method for forming gas pockets within integrated circuit devices to provide dielectric isolation between selected conductive structures in the integrated circuit device. The method is useable with many known integrated circuit manufacturing processes wherein the resulting device comprises, preferably, an uppermost layer of intermetal dielectric, on which the method of the present invention may be performed. In general, the method of the invention comprises the following steps. Providing an integrated circuit device structure with a top layer at least partly formed of a segregated conductive material and a solid dielectric material. Forming a mask over the top layer. Forming openings in the mask corresponding to positions where gas pockets are desired in the finished integrated circuit device. Etching through the openings in the mask to form gaps in the dielectric material of the top layer. Depositing a layer of dielectric material over the top layer to close the openings of the gaps formed in the dielectric material to create gas pockets or chambers in desired locations between conductive structures in the integrated circuit device.

Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets

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Fremont, CA, United States of America

Kurt Pang