Infineon Technologies Ag

Kurt Matoy

Markus Zundel

Dirk Ahlers

Thomas Krotscheck Ostermann

Peter Maier Brandl

Manfred Schneegans

Robert Illing

Bernhard Goller

Wolfgang Lehnert

Bernhard Weidgans

Juergen Steinbrenner

Evelyn Napetschnig

Paul Ganitzer

Markus Kahn

Martin Mischitz

Stefan Woehlert

Uwe Hoeckele

Johann Gatterbauer

Christian Djelassi

Michael Nelhiebel

Michael Rogalli

Herbert Gietler

Thomas Detzel

Sven Lanzerstorfer

Mark Harrison

Stefan Decker

Hubert Maier

Martin Sporn

Bernhard Auer

Arno Zechmann

Helmut Schoenherr

Christian Krenn

Silvana Fister

Christoph Brunner

Elfriede Kraxner Wellenzohn

A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280&#xb0; C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40&#xb0;.

Method of forming an aluminum oxide layer, metal surface with aluminum oxide layer, and electronic device

A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor. A method of producing the semiconductor device is also described.

Semiconductor device including an integrated resistor and method of producing thereof

A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

Semiconductor device including an integrated resistor

According to various embodiments, a semiconductor device may include: a contact pad; a metal clip disposed over the contact pad; and a porous metal layer disposed between the metal clip and the contact pad, the porous metal layer connecting the metal clip and the contact pad with each other.

Semiconductor device having a porous metal layer and an electronic device having the same

A method of fabricating a semiconductor device includes etching a first surface of a semiconductor substrate from a first side using a first etching process to expose a second surface. The second surface includes a first plurality of features. The first plurality of features has an average height that is a first height. The second surface of the semiconductor substrate is etched from the first side using a second etching process to expose a third surface of the semiconductor substrate. The second etching process converts the first plurality of features into a second plurality of features. The second plurality of features has an average height that is a second height. The second height is less than the first height. A conductive layer is formed over the third surface of the semiconductor substrate using a physical deposition process.

Metallization layers for semiconductor devices and methods of forming thereof

Semiconductor device including transistor device

A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.

Passivation layer and method of making a passivation layer

In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.

Layer stack

Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.

Integrated circuit including power transistor cells and a connecting line

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Strau, Austria

Kurt Matoy