Polar Semiconductor, Inc.

Allegro Microsystems, LLC

Polarfab, LLC

Kurt Kimber

David Litfin

Steven L Kosier

Joshua J Wibben

Joseph Burkhardt

Peter Tod

A switching regulator control circuit includes a circuit configured to generate a control signal to control conduction of the regulator switch in response to a reference signal that is ramped to control a rate of change of the regulated output of the regulator and the control signal is gated in response to a PWM signal.

Control circuit for a switching regulator driving an LED load with controlled PWM dimming

A circuit for protecting a metal oxide semiconductor (MOS) device is configured to hold down or pull down a voltage at a gate of the protected MOS device during an electrostatic discharge (ESD) event. The circuit includes at least one active device or capacitance-providing element connected to the gate of the protected MOS device, configured to pull down or hold down the voltage at the gate of the protected MOS device when the ESD event occurs.

Anti-snapback circuitry for metal oxide semiconductor (MOS) transistor

An over-current protection device for use in a switched mode power supply prevents over-current conditions caused by short-circuits faults. The over-current protection device monitors a current in the switched mode power supply, and in particular, determines a peak current value associated with the monitored current. The monitored current is compared to a reference value to determine whether an over-current condition exists. If an over-current condition is detected, then the over-current protection device modifies the 'off' time of the switched mode power supply based on the determined peak current value.

Over-current protection device for a switched-mode power supply

An antifuse device is constructed from a bipolar junction transistor (BJT). The BJT includes a collector, a base, and an emitter. In one embodiment the BJT is formed inherently within a field effect transistor (FET), including a first doped region, a second doped region, a gate, and a body region. The collector of the BJT is realized by the first doped region of the FET, the emitter of the BJT is realized by the second doped region of the FET, and the base of the BJT is realized by the body region. A high resistance path exists between the collector and the base. A first input voltage is connected to the collector and a second input voltage is connected to the base. A switch connects the emitter to a fixed potential when the switch is closed. The antifuse device is programmed by closing the switch and allowing the first input voltage and the second input voltage to create a large current from the collector to the emitter, through the base, such that the high resistance path between the collector and the base is converted to a permanent low resistance path.

Bipolar junction transistor antifuse

A system and method for dynamically protecting a vulnerable device from an ESD event includes an ESD event sensor and a breakdown voltage adjustment circuit. The ESD event sensor detects an ESD event and provides a signal to the breakdown voltage adjustment circuit indicating that an ESD event has occurred. The breakdown voltage adjustment circuit receives the signal from the ESD event sensor and adjusts the breakdown voltage of the vulnerable device during the ESD event.

Growing community of inventors

Minneapolis, MN, United States of America

Kurt Kimber